Clocksource for USB-Host (STM32H7)
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2020-04-26 07:53 AM
Hello,
I'm developing a USB-Host application (MSC / Fullspeed) with the STM32H743 µC (using STM32H743I-EVAL2 Board)
The application works fine when using PLL3Q as clocksource.
But when I use PLL1Q or RC48 as clocksource the USB "Core soft reset" timed out:
OTG->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; // Core soft reset
// Wait Core reset to finish, max 100 ms
tout_ms = 100U;
while ((OTG->GRSTCTL & USB_OTG_GRSTCTL_CSRST) != 0U) {
if (tout_ms == 0U) {
return ARM_DRIVER_ERROR_TIMEOUT;
}
tout_ms--;
HAL_Delay(1U);
}
HAL_Delay(1U);
I mapped RC48 to MCO1 to check if there is an 48MHz output and it is.
I checked the RCC/USB registers but couldn't find anything suspicious.
Does anyone has an idea what's wrong here?
Thanks,
Peter
Solved! Go to Solution.
- Labels:
-
RCC
-
STM32H7 Series
-
USB
Accepted Solutions
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2020-04-26 03:00 PM
HSI48 should be calibrated to some external source with the CRS peipheral, either to LSE or a SOF signal coming from another host. CRS is not running (APB1HENR = 0), LSE is not running (BDCR = 0), and there is no incoming SOF because you are the host.
This should not prevent an USB core reset though, but I am not exactly sure what an unconfigured CRS would do to HSI48. Anyway, not a healthy configuration.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2020-04-26 09:19 AM
Can you post the contents of all RCC registers for the working and non-working cases?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2020-04-26 10:51 AM
Hi,
sure, here is a picture, mapping all changed RCC registers just before the soft reset should occur.
On the left the working PLL3 configuration and on the right the non working RC48 configuration.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2020-04-26 03:00 PM
HSI48 should be calibrated to some external source with the CRS peipheral, either to LSE or a SOF signal coming from another host. CRS is not running (APB1HENR = 0), LSE is not running (BDCR = 0), and there is no incoming SOF because you are the host.
This should not prevent an USB core reset though, but I am not exactly sure what an unconfigured CRS would do to HSI48. Anyway, not a healthy configuration.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2020-04-26 03:28 PM
And what if you remove the timeout, does the reset hang forever?
JW
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2020-04-27 10:12 AM
You're right! After a complete power cycle, the USB with HSI48 worked for approx. 5 minutes, then the error came back.
When I think about it, it should be clear that the accuracy cannot be very high, because it's just an RC oscillator and USB has tight timing constraints.
Without calibration it's more like an adventure.
And the USB-PLL1 doesn't work because of a configuration mismatch (24 Mhz instead of 25Mhz HSE).
Thanks for the support!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content
‎2023-09-08 11:47 PM
In the RM043 it's not well explained how HSI48 (RC48) should be implemented, but it looks like without remote syncing it's not sufficiently accurate for high speed USB. I've been having difficulties getting the LTDC to 25MHz and keeping the core clock at maximum and USB at 48 MHz, so the HSI48 solved that, but clearly it's unusable without using the SOF (Start of Frame) sync input that appears when SOF is enabled for the HSI48 usage.