Well the usual case for ST to offer the Low Flash options / pricing stratification is that it takes significantly less time on the test equipment, and increasing the unit throughput.
The equipment is expensive, and so spending multiple seconds to erase, write and erase a 1MB part is going to be very significant. Price stratification allows sales to get design wins over competitors, or to sell more ST parts into a BoM. A $2 part that meets the customer's needs and removes a competitor is better than loosing a $20 sale. But in the current market the $20 part might now be an easier and more profitable sale.
I'm not sure what the failure rate is for STM32 die, and I don't know if there is any ability to remap the flash array such that they can find a good section.
Yes, the flash array will take a lot of space, the better route would be a die shrink with a smaller array, and many more die on the wafer, but there's also a lot of testing, validation and characterization involved. Not to mention the planning, scheduling, and inventory. I think the F722 was the smaller part/die.
With the advent of QSPI XIP there's opportunity to have flexibility in part sourcing, and very large FLASH, that can't be accommodated on-chip economically.
Value Line also gives the opportunity to disable externally sourced IP and things which must be licenced (patent pool, etc). ie USB, CAN, DSI, Ethernet, Crypto etc. Remove cost of those, and test time costs.
