Hello, I am using STM32F407ZGT6 and have the issue with time of RTC peripheral which resets to initial value after power down the board while VBAT pin is connected to CR1220 battery and LSE is used as crystal. How can I solve it?

[Aasda.3]

This is related part of the board.

[waclawek.jan]

How is VREF-P generated?

In any case, disconnect VDDA from VREF-P and connect it to VDD.

 

JW

[waclawek.jan]

See my reply at the thread end.

JW

[JTP1]

Pdr-on1 jumper is 1-2 ?

Boot1 jumper is 2-3 ?

Typically backup battery has also some parallel capacitor, 100nf or bigger. Maybe worth of trying to add.

22pf caps on 32khz crystal sounds bit high in capacitance.

[waclawek.jan]

> Typically backup battery has also some parallel capacitor, 100nf or bigger. Maybe worth of trying to add.

I vote against this. VBAT consumption is low, Li cell impedance is low, and any additional part is potential source of leakage i.e. shortened cell life.

JW

[Aasda.3]

VREF-P is generated based on VCC and TL431 for producing accurate voltage because of ADC refrence. (for this reason I separate VDD from VDDA )

Why should VREF-P be separated from VDDA?

In datasheet these are connected to each other.

I don't have any problem in other peripherals because of separating VDD and VDDA.

[Aasda.3]

Pdr is connected to VDD and Boot is pulled down.

I will add cap to VBAT pin for testing.

22pf is inside of the proposed range

[JTP1]

Ok👍 please note that you can have maximum 300mV difference between Vdd and Vdda. At least for testing, connect Vdd and Vdda to same supply.

[waclawek.jan]

> VREF-P is generated based on VCC and TL431 for producing accurate voltage

> because of ADC refrence. (for this reason I separate VDD from VDDA )

I've highlighed the requirements put forward in datasheet: VDDA should be connected to VDD in a way which ensures that there's no more than 300mV between them during powerup; and VDDA must also follow VDD during powerdown. A carefully designed passive filter (RC/LC) can be used to remove most of the HF noise.

VDDA is not the dominant contributor to ADC precision, VREF+ is. Btw. the 'F4xx are not very good in analog functions, the ADC is rather noisy anyway.

> Why should VREF-P be separated from VDDA?

> In datasheet these are connected to each other.

In models, where there's no separate VREF+ pin, it is indeed connected to VDDA - but there, too, VDDA must be connected to VDD.

Your problem is related to VBAT-domain reset. During powerup/powerdown, the switch which switches the VBAT-domain's supply voltage between VBAT pin and VDD, is controlled by the brownout/poweron-reset circuitry, which is derived from the VDDA domain. In other words, if VDDA is high while VDD is low, this switch is not disconnected from VDD, and there is a path between VBAT and VDD which pulls VBAT low (measure VBAT using oscilloscope during power-down/up) and that in turn causes the VBAT-domain reset.

JW

[Aasda.3]

Thank you do much. This is exactly what happens. In other words, connecting VDDA to VDD solves the problem.

About connection between VREF and VDDA for having exact voltage for ADC refrence what should be done if there is ripple on VDD (except of LC/RC filter)?