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Help on workflow for the software reset in ETH configuration



I started a post a week ago ( that has been viewed over 60 times without any reply, for finding a solution for this issue, I would like to know more details on the workflow of the software reset in ETH configuration:

HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
  uint32_t tmpreg1 = 0U, phyreg = 0U;
  uint32_t hclk = 60000000U;
  uint32_t tickstart = 0U;
  uint32_t err = ETH_SUCCESS;
  /* Check the ETH peripheral state */
  if(heth == NULL)
    return HAL_ERROR;
  /* Check parameters */
  if(heth->State == HAL_ETH_STATE_RESET)
    /* Allocate lock resource and initialize it */
    heth->Lock = HAL_UNLOCKED;
    /* Init the low level hardware : GPIO, CLOCK, NVIC. */
  /* Enable SYSCFG Clock */
  /* Select MII or RMII Mode*/
  SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
  /* Ethernet Software reset */
  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
  /* After reset all the registers holds their respective reset values */
  /* Why the SWR bit is already '1' before the following operation? */
  (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
  /* Get tick */
  tickstart = HAL_GetTick();
  /* Wait for software reset */
  while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
    /* Check for the Timeout */
    if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
      heth->State= HAL_ETH_STATE_TIMEOUT;
      /* Process Unlocked */
      /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are  
         not available, please check your external PHY or the IO configuration */

      return HAL_TIMEOUT;
  /*-------------------------------- MAC Initialization ----------------------*/
  /* Get the ETHERNET MACMIIAR value */
  tmpreg1 = (heth->Instance)->MACMIIAR;
  /* Clear CSR Clock Range CR[2:0] bits */
  tmpreg1 &= ETH_MACMIIAR_CR_MASK;

The SWR bit is already '1'  before it gets set at Line39 and this function call returns HAL_TIMEOUT at Line59.

As the application code runs correctly on a demo board with STM32F407ZGT6 from a manufacturer,  therefore we designed a test board with STM32F407ZGT6 for this ethernet application, and runs the application code without any modification (i.e. the same pin configurations and same clock rate), however, we got the same issue on software reset.

Anyone knows the detailed workflow of this software reset:

1. Is it abnormal that the SWR bit is already '1' before it gets set at Line39?

2. After the SWR bit is set, it keeps checking whether this bit is cleared until time out, so what are the operations  that clear this bit? and what is the sequence of these operations?

3. Does it involve any interactions from external PHY chip? If yes, then which pin we should examine with a scope? We checked the REF_CLOCK with a scope, it's a 50MHz clock signal.

Any reply would be highly appreciated.