DMA 1Mbit/s Interprocessor Communication STM32H755

[bock]

Hey everyone,

(code is attached to the post)

I'm currently working on a project and using the NUCLEO-H755ZI-Q development board.
A part of this project contains datahandling between the M7 und M4 Core. Therefore I read through a lot of documentation and tried out HSEM (which works great, but needs the CPU to handle, which is not optimal for my usecase) and DMA Handling with using the D3 sRAM Domain.

My problem seems to be, that I'm not able to generate an interrupt / callback on the other core (e.g. the M7 core handels data over DMA into the sRAM and a callback on the M7 ist thrown on completion. I'm able to debug as far, that I can see, that both the M7 und M4 can see the data correctly written into the RAM thanks to MPU configuration.)

What I need - or more like I think I need - is a way to generate an interrupt or callback on the M4, so I knows to get the new data and work with it. (and yes I future also the other way round from M4 to M7)
Maybe there is a better way to handel my problem - if so, please let me know.

Thanks you in advance for your time!

[TDK]

Use the send event (SEV) instruction to send an event to the other core to trigger an interrupt.

https://www.st.com/resource/en/application_note/dm00771441-stm32h745755-and-stm32h747757-lines-interprocessor-communications-stmicroelectronics.pdf

[bock]

Hey TDK,

thank your for your quick response.

Does that mean, that I use DMA as described and use SEV inside the DMA Callback to send an interrupt to the other core?

kind regards, Bram

[TDK · Accepted solution]

Yes. And ensure you are using proper cache management, or disabling it.

After data is written, use SEV to tell the other processor to process that data.

You shouldn't really need DMA to share data. Both chips can see (mostly) the same memory addresses. You can reserve a chunk for use by both cores for sharing data.

[bock]

Thank you very much! Ill try that asap

[marcus2]

Hi TDK,

I just see that the AN5617 you referenced explicitly recommends DMA/MDMA in section 3.3.3.
Would you say that the cpu offloading effect is not very relevant in the dual core architecture given?

Is there any example code that shows how such an MDMA-DMA chain between the M7 and M4 cores could be realized?

Sorry for my stepping in: Bram is a close colleague, we are working together.

Kind regards

Marcus 

[TDK]

> Would you say that the cpu offloading effect is not very relevant in the dual core architecture given?

My main point is that if data is available to the M4 core, it's already available to the M7 without moving it, and vice-versa (except for some special memory locations). No DMA/BDMA action necessary. You just need to know where it is in memory. You can do this with a memory pointer set to the same location on both cores, and with that space carved out in the linker file so it's not assigned to anything.

// on both cores
volatile uint32_t* big_buffer = (volatile uint32_t*) 0x20000000;

// on sending core
big_buffer[0] = ...
etc...
// send SEV event

// on receiving core
// (in reponse to SEV event)
uint32_t data = big_buffer[0];
etc...

If for whatever reason you want to copy data, DMA/BDMA can be used to free up the CPU, but how much it matters will depend on how much memory you're transferring and how much extra CPU usage you have. I imagine it is negligible for the majority of applications.