ST25RU3993 higher than expected power on RX

[SZhen.3]

Hello,

I'm currently prototyping a custom design utilizing the ST25RU3993 which should be nearly identical to the reference design HPEV. I've removed the external PA and 2nd antenna, but otherwise the design is very similar. I've attached the schematic for comparison. Where available, I've followed the reference layout as closely as possible.

The board is showing poor read rates (low distance, ~50% success rate for consistent tag-antenna positions) which I suspect is the result of the following: the RX probe point (equivalently RF-TP4 on the eval kit) shows almost 5dBm at the carrier frequency when measured with the spectrum analyzer. I understand this should be closer to -14dBm.

Am I missing something obvious from my design? Or could this be a possible result of an assembly issue? Looking forwards to any insight into the issue or further testing I can perform.

Thanks!

[Bart Herse · Accepted solution]

Hello SZhen.3,

I have reviewed the attached schematic and here's what I have found:

1.)

The loop filter circuit (C19, R2, C20) which is connected to the pin LF_CEXT shows different values.

This is a significant change and affects the RF carrier (this part of the schematic should be moved to the RF section of your schematic - just for clarity)

The values of the loop filter, shown in the reference design should be kept.

2.)

There are a changes of the capacitance values of

C31, C32, C33, C43 (10nF --> 100nF) !!

C3, (100nF --> 82pF) !!

These differences and others (not complete list) might not be related to your topic at hand.

C15, C35, C38, C42, C44, C27 (120pF --> 82pF)

C13, C72, C74, (30pF --> 82pF)

If you have multiple boards showing the same kind of performance drop then I would say the likelihood of a random assembly issue is low.

The issue you might having does sound as if the carrier cancellation circuit (=CCC: U2, U3, U4) was not tuned / adjusted. Is this feature already implemented in your FW? If not then for initial testing purposes you might consider disconnecting the CCC and replace it with a 50 ohm termination. If done so check the reflected power at J3 again.

I am assuming that an antenna suitable for UHF RFID has been connected to the antenna port.

Cheers,

B

[SZhen.3]

Hi Bart,

Thanks so much for looking through and catching some of these details!

1.)

I was originally worried that the LF_EXT value changes would negatively impact the design, but was able to run auto VCO tuning and the chip indicates OSC stable and PLL locked. Is there anything else I should closely monitor to perhaps rule this out as a potential cause? I will also test switching back to the reference design values.

2.)

Very embarrassing on my part for the capacitors with significant differences. I have corrected them on the prototype boards. This does not seem to have helped rectify the problem.

I did switch from 120pF to 82pF since the package size changed on my design, so I was attempting to maintain an equivalent impedance profile. I will look at substituting the 30pF capacitors in a similar way.

The cancellation stage was not tuned. I assumed the default values (0.9pF) + passives centred the pi-filter around 50Ohms. After swapping to a 51Ohm termination resistor, the reflected power measured at ~ -1dBm, so slightly better. I will look at implementing CCC tuning. I'm surprised it would have such a large impact when using the internal PA, as when I set the dev-kit CCC values to get a similar amount of reflected power, read rates are still significantly better.

I am using the same antenna that came with the dev-kit.

[Bart Herse]

Hello SZhen.3,

concerning the loop filter. If the TX spectrum looks clean and regulatory requirements can be met and locking time of the PLL is fast enough across the frequency range, then you might keep your loop filter design.

Unless you encountered some issues I still recommend the loop filter from the reference.

Cheers,

B