Posted on January 19, 2007 at 06:26I all ready know that. What I mean is this, since CE goes down until CE goes it is 15.62 ns, which is the access time. That’s the time I’m referring, not the total time to read data, which is as you said 31.2ns. The thing is that my SRAM is 10ns access time, so from CE going down to Data present on the output there is no more than 10ns. With 0 wait states, the STR7 have 15.62 ns until it reads data, but in that case it reads wrong data. I need 1 wait state, which means an access time of 30.2ns from the SRAM point of view, but that makes no sense, also when looking with the oscilloscope the signals are in the right places, I mean, with 0 wait states, if I look to D0 and with the debugger I try to read one position of the SRAM, the oscilloscope shows a logic 1 5ns before CE rises, but the STR7 reads a logic 0. That’s what I can not understand.
