Unable To Halt ARM Core, STR710

[selaslan]

Posted on October 13, 2009 at 18:49

Unable To Halt ARM Core, STR710

[selaslan]

Posted on September 04, 2009 at 14:41

Hi,

I'm developing a network door access controller based on STR710FZ2 I have designed my own PCB and manufactured 5 samples of this board. When I want to start to run my code, I always receive ''Unable To Halt ARM Core'' message, I'm using IAR V5.11 compiler I have downloaded latest version of J-Link drivers from Segger. I have tried to reset via J-Link Commander and J-Link Flash utility. But same result. I have attached some screenshots related to my tryouts Can you help me how can overcpme from this issue Selahattin Aslan selaslan@gmail.com ________________ Attachments : IAR_Compiler_-_Error.bmp : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtJe&d=%2Fa%2F0X0000000aLW%2FSJyizZHSFZ_FhIRmeJsE4NcKGt5tGT4rEmYnjAyfbnI&asPdf=falseJLink_Commander_-__Error.bmp : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtSB&d=%2Fa%2F0X0000000aQD%2FJIH3zIU3ztT3z1wPn64AvfVaBXDzEicrIw3fukKWwOY&asPdf=falseJLink_Flash_-__Error.bmp : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtRT&d=%2Fa%2F0X0000000aQ6%2Ftq5pj0ryf2S92rp4OQ0c9GX5oj8EIUMj4GgKbD2.SgU&asPdf=false

[tomas23]

Posted on October 13, 2009 at 18:49

Check the reference schematics of ST evaluation boards for the complete JTAG connection. The nJTRST and nRST signals have to be well implemented, too.

If you already have some code in FLASH, try to change boot settings to RAM and try to connect again. Otherwise attach your schematics. [ This message was edited by: edison on 13-10-2009 22:20 ]