Problem with EMI address bus in reset state, clamping bus signals

[richardmauruschat9]

Posted on May 04, 2007 at 12:39

Problem with EMI address bus in reset state, clamping bus signals

[richardmauruschat9]

Posted on May 03, 2007 at 08:35

Hi,

I'm having some problems with the STR710FZ2T6 relating to the external memory interface. During periods of operation where other parts of our system are accessing the memory bus, we force the ARM External Mem Interface (via register PCU_RSTR bit2 )into it's reset condition (input with weak 100k pulldown) so it should appear passive to other bus activity. The Data bus is fine, but the Address bus gets clamped at 2.7V by the STR710 address bus EMI (vcc is 3.3V) - consequently the STR710 and external bus driver devices (supplied from the same 3.3V vcc) see excessive power dissipation and temperature rise. I can't see any other way we can set the bus into a passive state, or methods of solving the problem, except maybe using a 3.0V Vcc instead of 3.3V and ultimately connecting series resistors in the address bus.. Any thoughts appreciated Cheers Rich :D

[kleshov]

Posted on May 04, 2007 at 07:16

Quote:

On 03-05-2007 at 12:05, richm wrote:

we force the ARM External Mem Interface (via register PCU_RSTR bit2 )into it's reset condition (input with weak 100k pulldown) I would expect the address bus pins of the MCU to be push-pull outputs only. Nowhere in the manual have I read that they are weak pull-down during reset. I think the right thing to do is to use output buffers with hi-Z capability on the address bus. Regards, - mike

[richardmauruschat9]

Posted on May 04, 2007 at 07:44

From page 49/262 of STR71xF microcontroller family Reference Manual UM0084:

2.6.8 Peripheral reset control register (PCU_RSTR) Bit 2 EMIRST: External Memory interface reset 0: Normal EMI operation 1: Force External Memory Interface to reset state. Reset activation/ deactivation is synchronous with system clock MCLK.==================================================================== From page 19/74 of STR71xF datasheet for device pinout function: Note 7) relating to reset state of Address pins A0-A19: 7. During the reset phase, these pins are in input pull-down state. When reset is released, they are configured as Output Push-Pull.============================================================= unfortunately I am very restricted for space, and physically finding space for additional buffers is impractical :(

[richardmauruschat9]

Posted on May 04, 2007 at 12:39

whilst the Reset pin is held low, the Address bus is definitely configured as inputs with soft pulldown as advertised, that much is measurable.

However, the question is more relating to the EMI Reset register functionality - is setting bit2 of PCU_RSTR supposed to reset the output structure to the same state as suggested from the datasheet statement: ''1: Force External Memory Interface to reset state.'' , or just to some arbitrary ''reset'' state of output low???