Posted on May 17, 2011 at 09:45Hi,
We are using UART2 in STR910FAM32 to read a string of data. For each byte of data read we need to detect the parity error (if any) - this we do by reading the Parity Error Bit in the Raw Interrupt Status register. If the Parity Error is detected we need to convert the RX pin to a GPIO pin and force it logic low between 0.2 to 0.7 of the Stop Bit time. Since we are changing the state of the CPU pin to a GPIO Output instead of UART_RX before the CPU has completed the data reception, what is the logic level that the internal UART will see i.e. is it internally pulled up or pulled down. Unfortunately we cannot use the Interrupt mask register PE bit to detect the parity error as this gets set after the stop bit has been rece'd.
Thanks.
