Posted on May 17, 2011 at 09:54Hi, We are seeing a strange issue and were wondering if this is a bug. We are using STR910FAM32 device (Rev G silicon) and programming secondary FLASH by running code in Primary FLASH. When we enable EN_PFQBC bit in SC...
Posted on May 17, 2011 at 09:54Hi, We are using STR910FAM32 and we are using the SRAM for code and data storage. From the Data sheet it appears that the SRAM is mapped in three regions: 0X0400 0000 - SRAM D-TCM 0X4000 0000 - SRAM, AHB BUFFERED 0X500...
Posted on May 17, 2011 at 09:51Hi, Here is the snippet of the code where this normally occurs. When an error occurs, the processor would hang. This issue only occurs when 'addr' points to start of the secondary FLASH. The other points to note: 1. Co...
Posted on May 17, 2011 at 09:51Hi, We have seen similar issues while running code on STR910FAM32 (Rev G) silicon. The FMICLK = RCLK = 96MHz and waitstates is set 2. Every once in a while we see an issue when we are reading data from the secondary FL...
Posted on May 17, 2011 at 09:45Hi, We are using UART2 in STR910FAM32 to read a string of data. For each byte of data read we need to detect the parity error (if any) - this we do by reading the Parity Error Bit in the Raw Interrupt Status register. ...
