Posted on June 01, 2006 at 09:34Hi.
I am developing a hardware design with a STR710F (running at 64MHz) that needs external Flash (on CS0 and CS1) and SRAM (on CS2), so I need to use the EMI, and I have found a lot of 'little details' that I don't understand. I use as a guide the 'STR710F Datasheet rev. 7' and the 'STR71x Microcontroller Reference Manual rev. 7' and lots of SRAM and Flash datasheets. Also, my company has purchased the STR710-EVAL; I will talk about that later.
First off, in the reference manual, page 24, when you want to make a write-single cycle access, the length that a single access will require is 'CSn[3:0] length (Write) = C_LENGTH+1'... but if you look at fig 3 (pag 26), seems to be 'CSn[3:0] length (Write) = C_LENGTH+2'. It leads that the minimum write-single cycle access (with 0 wait states) will be 2 clock cycles.Is that correct?
In addition, in the STR710F datasheet, we can find several timing figures (from fig 10 to fig 17) that the MCLK signal is not present, making more difficult to understand the bus cycles. Also, I think that are (at least) one mistake. In fig 10, trds (read data setup time from table 21) says that its value is tc (memory cycle time wait states) so, that means that data must be present since the moment we assert the RDn signal (as trp is also tc). ?????? The value of trds should be tmclk, is that correct?
Another question is related with trdh (read data hold time) in the same fig. In table 21 says that its value must be 2ns, but if I should use the flash memory installed in the STR710-EVAL (M28W320CT from ST) when I look in the M28W320CT datasheet, you notice that fig 10 and Table 15 says that parameters tEHQX, tAXQX, and tGHQX are 0ns.??????? This means that as soon I deassert any control signal of the memory, the data on the bus will desappear in 0ns. How can you use that memory in the design without any kind of logic gates to delay the control signals?
More generic questions:
· Is generated any clock cycle between two consecutive reads but over different CSx?
· Is generated any wait state if a particular SRAM keeps data floating in the bus more time that required (typ 25ns)?
· Is there any more acurate timings (maybe with more CS signals in one fig and the MCLK signal)
Ufff... as a first approach, I think it is enough...although there are more questions I will post here...
Sorry if the message is not so clear as I would like, because it's quite difficult to explain the doubts I have right now.
Can anybody help me?
Thanks
