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Core Configuration and Inter-Core Communication on SPC58EC80E (SPC58EC-DISP)

mmansouri
Associate II

Hi ST Community,

I'm working on a project using the SPC58EC80E microcontroller on the SPC58EC-DISP board.

I'm particularly interested in optimizing the configuration of the two cores (e200z420n3) and understanding their inter-core communication mechanisms.

Specific Questions:

  1. Core Configuration:

    • What is the most efficient way to configure the two cores for optimal performance?
    • What factors should be considered when determining the core clock frequencies and priorities?
  2. Inter-Core Communication:

    • How can I effectively implement inter-core communication between the two cores?
    • Are there specific mechanisms or protocols recommended for this purpose?
    • How can I ensure synchronization and data consistency between the cores?
  3. FreeRTOS Usage:

    • Can I utilize FreeRTOS on both cores simultaneously?
    • If so, what considerations should be made for task scheduling, resource sharing, and inter-core communication?
    • How can I configure the FreeRTOS kernel to take advantage of the dual-core architecture?
  4. Core Process stack Size, IRQ Stack Size and load address:

    mmansouri_0-1730296978407.png
    • What is the significance of the "Process stack Size" and "IRQ Stack Size" parameters?
    • How do these parameters affect the performance and memory usage of the core?
    • What are the recommended values for these parameters in different use cases?
    • What is the purpose of the "Load Address" parameter?
    • How does it influence the memory mapping and code execution of a process or task?
    • How should this parameter be set to ensure correct execution and avoid memory conflicts?

I would be grateful for any insights, code examples, or best practices that can help me optimize the performance and reliability of my application.

1 REPLY 1
mmansouri
Associate II

@Max VIZZINI@Peter BENSCH@Erwan YVIN  if you can help me about this topic, thanks in advance.