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LSM6DS3: What exactly does SW_RESET do?

IDEngineer
Associate II

The LSM6DS3 has two "reboot" style operations. I've read spec sheets and appnotes but can't find a clear description of one of them.

BOOT (CTRL3_C bit 7) appears to freshly load the "trimming parameters", which I presume are factory values written to compensate for normal production variances. BOOT does not sound like an actual "reboot" (like a power cycle) of the device.

SW_RESET (CTRL3_C bit 0) is described as "software reset", which sounds like the equivalent of a power cycle. However the spec sheet also mentions "after next flash boot", which makes it sound like more than just a power-cycle equivalent. If SW_RESET is indeed the same as a power cycle, you'd think it would also load the trimming parameters. Yet the appnote says the following:

"The reboot and the sw reset must not be executed at the same time (do not set to 1 at the same time both the BOOT bit and SW_RESET bit of CTRL3_C register). The above flows must be performed serially."

...which makes it sound like SW_RESET does *not* reload the trimming parameters, and you must do that manually before invoking SW_RESET.

So: What does SW_RESET actually do, if it's not the same as a power cycle? To actually duplicate the behavior of a power cycle, is it necessary to command both a REBOOT and a SW_RESET in that order?

Thanks!

7 REPLIES 7
Eleon BORLINI
ST Employee

hi IDEngineer, did you tried the procedures for the boot described in the AN4650 p.61?

Reboot flow is as follows:

1. Set the Gyroscope in Power-Down mode;

2. Set the Accelerometer in High-Performance mode;

3. Set to 1 the BOOT bit of the CTRL3_C register;

4. Wait 20 ms.

Reset flow is as follows:

1. Set the Gyroscope in Power-Down mode;

2. Set the Accelerometer in High-Performance mode;

3. Set to 1 the SW_RESET bit of the CTRL3_C register;

4. Wait 50 μs (or wait until the SW_RESET bit of the CTRL3_C register returns to 0). 

Regards

IDEngineer
Associate II

Thank you for responding!

Yes, I have AN4650 open on my second screen along with the spec sheet and am carefully paying attention to what they both say.

My question is not HOW to do a SW_RESET, but rather WHAT specifically is the difference between a "SW_RESET" (CTRL3_C bit 0) and a "BOOT" (CTRL3_C bit 7). And, as I asked above: "What does SW_RESET actually do, if it's not the same as a power cycle? To actually duplicate the behavior of a power cycle, is it necessary to command both a REBOOT and a SW_RESET in that order?"

Thank you for any additional clarification you can provide on exactly what each of these commands do, and how they differ from each other.

Eleon BORLINI
ST Employee

The boot procedure allows you to reload the calibration parameters in the LSM6DS3 registers; it is not like a power off, and so for example the device operating mode doesn’t change after boot (if before was e.g high performance mode, it will remain hp mode). The SW reset is more like a power toggle, so you reset your device even if Vdd is still on. Regards

IDEngineer
Associate II

OK, thank you for the clarification.

If the SW_RESET is "more like a power toggle", then does it also "reload the calibration parameters" like a power toggle does? In other words, does SW_RESET automatically include a BOOT procedure too? Or is it necessary to do both?

Eleon BORLINI
ST Employee

Hi IDEngineer, yes the SW_RESET should include the BOOT procedure too, but if you want to do a RESET it could be more indicated to put 1 both SW_RESET and BOOT bits in CTRL3_C  reg. Regards

IDEngineer
Associate II

Hmm... your appnote AN4650, page 61, says:

"In order to avoid conflicts, the reboot and the sw reset must not be executed at the same

time (do not set to 1 at the same time both the BOOT bit and SW_RESET bit of CTRL3_C

register). The above flows [BOOT and SW_RESET] must be performed serially."

Eleon BORLINI
ST Employee

​Sorry I did't meant to write e.g. 81h CTRL3_C, but put both bits at 1. Then it's better to follow sequentially the two procedure with the described timings, but a simple SW_RESET should be enough. Regards