Hello all,
I am developing a vibration measurement device using LSM6DS3TR-C. Most of the time the data were in good shape (99%). However, I noticed some spike in my vibration intensity reading randomly. After checking the raw data I saw some step change at the same time point, indicating the data reading of the three axis are confounding.
My configuration only requires the accelometer readings to be cached in FIFO:
1. enable block update
2. set fifo accelometer decimation register to 1 (no decimation)
3. set fifo accelometer data rate to 3333Hz
4. set accelometer data rate to 3333Hz, bandwidth 1.5khz, LPF_BW_SEL to 1
5. set FIFO mode to bypass, then set to FIFO mode (clear and restart FIFO)
6. polling FIFO_STATUS2(0x3B) register for FIFO_FULL_SMART.
7. I2C bulk read the FIFO for 682(sample count) * 3(axis) * 2(16bit-axes) = 4092 bytes from buffer
8. repeat from 5.
To identify the issue, I changed step 7 to the following:
For i-th reading
7.1 Read the FIFO pattern register (FIFO_STATUS3/4)
7.2 if i mod 3 != the pattern, print some log. otherwise read the FIFO register and make use the value.
7.3 Repeat 7.1 until the FIFO is depleted.
This captures the moment when the axis data getting misaligned. However, this makes the FIFO reading takes much longer (1.2s) than bulk reading (300ms), making it undesired for my application. However, I haven't come up with a reliable detection mechanism for the bulk reading to tell that axis misalignment occured. I checked all status registers and they were exactly the same on both situations.
After searching for this forum, there are plently of pending questions about the mistaken/interleaved/buggy FIFO reading. For example,
1. https://community.st.com/t5/mems-sensors/lsm6ds3-fifo-corruption/m-p/694386
2. Issue with Misaligned Accelerometer and Gyroscope ... - STMicroelectronics Community
3. LSM6DSM- Incorrect Accel Data on high ODR using FI... - STMicroelectronics Community
4. FIFO Corruption on LSM6DSM - STMicroelectronics Community
5. LSM6DS3 FIFO data corruption on random basis. - STMicroelectronics Community
......
Could ST confirm that, it is NOT guaranteed that the FIFO are pushed sequentially in a deterministic fashion, i.e., one MUST read the FIFO pattern (FIFO_STATUS3/4) before reading each data from the FIFO register (FIFO_DATA_OUT_L/H) to ensure what the next data is, and I2C bulk from FIFO does not guarantee the cyclic pattern of the reading?
If so, I think this should be put on the box! Please mention this on the application note or datasheet.
