Hello, ST Staff,
I have collected all information from internet about the misalignment buffer issue and tested out every method suggested by ST members (using ST library, BDU=1, IF_INC=1, watermark, continuous mode / fifo mode, etc.). And I am still stuck with this bug.
When using 3332Hz and FIFO I could never get a clean multi-FIFO reading that does not misalign. Checking the fifo pattern wont work as this shift happend in the middle of batch reading, not at the start. If I need to check every pattern when reading out the FIFO, the I2C won't keep up. Even if the IO was fast enough, what should we do to deal with the missing/disordered sample? Do we have to drop the whole data and resample a new piece?
In fact, after reading the forum post LSM6DSM - Page 1, Now I believe there is firmware/hardware bug in the LSM6 series that was never documented or addressed. This waste tons of our time. If you search for FIFO, almost all post are frustrated about the problematic FIFO reading but NONE of them could fix the problem nor can any provide a constructive suggestion. Can someone from ST please clearify whether this problem is a hardware bug? If so we will avoid choosing this series for the multi-FIFO sampling purpose!
For those who reached here after searching. I have my final conclusion: the LSM6 is NOT suitable for using FIFO to acquire multiple FIFO data due to racing condition of concurrent FIFO writting from sensor and FIFO reading from the controller. The ONLY approach that gave me steady clean waveform below is to use spinlock (busy wait) + reading the output registers (28h). It seems 3332Hz ODR is already too much for polling STATUS_REG for new data and one has to control the read-out timing by utilizing the delay timing. I would say it is a huge bummer for this product. After all it failed what the FIFO was designed for: NO BUSY WAITING!
