LIS3DH breakdown

RChau.1 · ‎2020-02-11

Hi,

I am using LIS3DH for a while now, on different custom boards.

I recently faced a major issue with it, which applied to all our last batch of devices (50 units).

At some point, the INT1 broke (not emmiting int signal) and power consumption raised to 70mA..

I set the logic of int pins to active low when the program starts.

After some testings, I figured out that without putting logic to active low (0x02 on CTRL_REG_6) the power consumption coomes back to normal. but int1 is still not working.

Regarding hardware, LIS3DH is implemented with these passive components:

100nF and 10uF between Vdd and gnd supplying pins VDD & VDDIO
47k pullup resistors for CS, INT1 & INT2
22Ohm line resistors for MISO MOSI and SCLK

Using new boards with same hardware for the first time with the same software works properly, until some point. Therefore it seems it is a hardware issue.

Would you have any idea where this issue could come from?

Best regards

Ozone · ‎2020-02-11

> Using new boards with same hardware for the first time with the same software works properly, until some point. Therefore it seems it is a hardware issue.

> Would you have any idea where this issue could come from?

Through overstressing the device in the assembly process ?

RChau.1 · ‎2020-02-11

Thank you for your feedback.

That is indeed something I thought of. Do you think it could be an explanation even if devices have this issue only after some time?

Eleon BORLINI · ‎2020-02-11

Hi @RChau.1 , are Vdd and VddIO same level and compatible with the master SPI? Did you manage to capture the SPI pattern during the failure event? Regards

RChau.1 · ‎2020-02-11

Hi,

The board has only one logic level which is 3.2V (including Vdd and VddIO). This batch of devices is the last iteration with minor changes (connectors and antennas) of a device we tested for a while now. This is the first time we get such issue. We set the device for interrupts only, and never directly read acceleration values. I did not get SPI pattern during failure but that is something I can dig into.