STM32 MPUs Products and hardware related

I am using STM32MP235 on custom board. At some point, I wanted to update the firmware via SFU using STM32CubeProgrammer.I rebooted the board in USB mode (setting the boot mode to BOOT using the pins) and launched CubeProgrammer.TF-A-programmer-usb loaded onto the board normally, but after that, the board stopped responding via DFU.After a power reset, the board boots in DFU mode, even though the internal eMMC contains the old firmware, and the default boot mode is eMMC.As soon as TF-A is loaded onto the board, the board disappears. Nothing is written to the debug port, making it seem as if TF-A failed to boot.I tried using ROMTrace TF-A. The behavior is exactly the same, and no trace is output to the port.Pin PG4 (FAILBOOTN) is connected to a red LED. During normal boot, this LED starts blinking, and after flashing the TF-A (whether via USB or Serial), it turns solid.The documentation says that the FAILBOOTN LED blinks when the board initially boots in USB/UART mode, meaning it doesn't

Does the ST LINK v2 support STM32MP235F connection?

Failed to set local time on STM32MP257.Firstly, I tried to use the commanddate -s "yyyy-mm-dd xx:xx:xx", and system can successfully return the time I set. But when I again use “date” to get the local time, system still return the wrong time in 2024.Then I tried to write into RTC, but still failed.Now because of the failure of time setting, all the apt command are unavailable.So I want to know how to correctly change the local time and RTC time, or to find an alternate way to apt-get package.Thank you.

I am currently using the distribution version: V5?rt 6.1.82-rt patch?stm32mp257 I am using the TSN mode of the STM32MP257 switch and found that once I set the date, it reverts to the time before the setting after a period of time, and also causes a probabilistic hang during shutdown or reboot. After investigation,this is caused by the deptp service being enabled in the TSN service. My current application only uses the switch mode and does not require TSN. Is it appropriate to disable deptp? What other services can be disabled to enhance system stability?  

I would like to gather information on the following points. Kindly guide me on these aspects:Identify the CMOS image sensors supported by the STM32MP255F and STM32MP257F. Determine whether the VB66GY and VB16GZ sensors are compatible with the STM32MP255F and STM32MP257F, including the required driver-level integration and software support.

Hi:Does I have STM32MP257F-EV1 board and another board can generate BT.656 video source without I2c setting.I want to use DCMIPP parallel interface to get the image. I modify the device tree in stm32mp257f-ev1.dts/ {... clocks { cec_clock: cec-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <12000000>; }; dummy_cam_clk: dummy-cam-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <54000000>; }; pad_clk: pad-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <100000000>; }; };...};&dcmipp { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dcmipp_parallel_pins_a>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dcmipp_parallel_in: endpoint { remote-endpoint = <&dummy_camera_out>; bus-type = <6>; bus-width = <8>; pclk-sample = <0>; }; }; };};&

Hello Team, On the Development Board, pin PN12 is used to detect whether an SD card is inserted or not; however, it is also required by xspm_p2_ncs, so I don’t think we can simultaneously use XSPIM1, XSPIM2, and PN12. Is there any other pin you would recommend for the purpose of detecting an SD card? Also, I am using the mechanical switch to detect the SD card. In the Datasheet, SDMMC1 is specified for the SD card However, in the AN5967 Document, SDMMC2 is preferred for the SD card. Which port, SDMMC1 OR SDMMC2, is preferred for a microSD card? Thanking you 

Hello Team, I am using STM32N657X0H3Q, I am planning to integrate external RAM; however, the mentioned standard PSRAM, APS256XXN-OBR-BG, is not readily available on the market, so I chose to upgrade to DRAM, APS512XXN-OB9-BG. Is this upgrade safe? Also, are there any alternatives to MX66UW1G45GXDI00 that can serve as a good NOR flash? Regarding the USB-C connection, I am using a much simpler structure here, where I have left the VBUS Floating(I do not intend to use this USB to drive anything or for power delivery, just using it to communicate with pc and STM32CubeIDE) as shown in the picture below. Can you please let me know if this is a viable USB connection and if it's good enough for communication with STM32CUBEIDE ? Thanking You

Hi All!I have successfully run ptp4l as a GM role on the 157d-dk1 kit, using NMEA+GPS in as a reference time. I have a specific setup, where NTP is actually disciplining the system clock and the PHC clock is driven from the CLOCK_REALTIME using phc2sys.I wanted to test the PPS output generation on the PG8 pin, so that I can compare incoming PPS with generated PPS, but I can’t make it work.The board version is C03 (no missing solderbridge), Yocto is Kirkstone (kernel 5.15), ptp4l 3.1.1.I have added PG,8,AF11 to kernel’s device tree (in separate inc file):    ethernet0_rgmii_pins_a: ethernet0-rgmii-0 {        pins4 {                pinmux = <STM32_PINMUX('G', 8, AF11)>; /*PPS OUT*/        };   }; Now I can see in gpioinfo output that it is used by kernel but still set as input.Then tried setting period for the PPS through ptp0 (tried different settings):echo “0 0 0 1 0” > /sys/class/ptp/ptp0/period The “clk_summary” shows and in general ptp4l works:          ethptp_k           

HiI designed a PCB with an STM32MP157 using a Micron LPDDR3 memory. When I started the layout, I was advised that the memory would be available at least until 2029, so proceeded in good faith. When I came to order prototype samples back in March, I found that there was a Last Time Buy of August 31st this year.The only option that I had was to change the layout to support DDR3L memory, however with the current DRAM supply crisis, I do not have confidence that this generation of device will have sufficient longevity of supply to justify the investment in mass production.My alternative is to jump to an STM32MP2-based board and use DDR4 or LPDDR4 memory which will likely be available for longer but again with the current supply chain situation, these generations could also be obsoleted sooner than anticipated. I already read of DDR5 and LPDDR6 memories coming on stream.Two questions:With regard to the STM32MP1 and STM32MP2 processors, what is ST’s best guidance about which DRAM memory type

Hi, I am trying to design a custom board with a 1 rank dual die 16Gb LPDDR4, AS4C1G16MD4V-046BIN. I have read the design guide AN5489 and DDR config AN5723. From my understanding there is only one chip select pin for each rank, correct? What do I do? Is there a configuration supported by the STM32MP2x processor with 2 chip select in 1 rank?FYI, I am designing a board based on STM32MP235, so supposedly only 1 rank is usable as per the datasheet.

Hi team ST,As we all know, the major DRAM manufacturers have all announced they will stop fabricating the DDR4 die and only LPDDR4 is still in production, in light of this, does STMicroelectronics has an plan to design a new PMIC more focus on the LPDDR4 configuration with less LDOs and smaller package? Given that we don’t need the external termination for DDR anymore with LP DRAM.

OpenSTLinux: Starter Package, plain image (FlashLayout_sdcard_stm32mp257f-dk-optee.tsv), version 5.0.17-openstlinux-6.6-yocto-scarthgap-mpu-v26.06.10M33 firmware: Zephyr RTOS (4.4.99), board target stm32mp257f_dk/stm32mp257fxx/m33, loaded and started from Linux via remoteproc.Goal: Drive a SPI device (Qorvo DW3000) from the Cortex-M33 over SPI6, which is exposed on the CN5 header (GPIO10/SPI6_MOSI = PC7, GPIO9/SPI6_MISO = PC4, GPIO11/SPI6_SCK = PF7).When the M33 firmware performs a SPI transfer, the GPIO chip-select line toggles correctly (verified on a logic analyzer), but SCK never produces any clock pulses & the line stays flat. Consequently no data is exchanged (MOSI/MISO flat). The transfer call itself returns; it just produces no clock.What I have already checked:-RIFSC firewall: SPI6 shows as NSEC, NPRIV, CID filtering disabled (from the RIFSC debug dump) — i.e. not blocked/assigned exclusively to the A35.-Clocks: clk_summary shows both ck_icn_p_spi6 (~200 MHz) and ck_ker_sp

Hello,I'm working with an STM32MP257 and encountering unexpected behavior regarding RTC resource isolation between the Cortex-M33 (bare metal/HAL) and Cortex-A35 (OpenSTLinux).I performed a simple test where my Cortex-M33 requests the initialization resource using the Resource Manager and holds it while reading the time registers:ResMgr_Status_t st = ResMgr_Request(RESMGR_RESOURCE_RIF_RTC, RESMGR_RTC_INIT_RSC);if (st == RESMGR_STATUS_ACCESS_OK){// Reading registers directly while holding the lockuint32_t tr = RTC->TR; uint32_t dr = RTC->DR;// ... intentionally omitting ResMgr_Release to test the lock ...} While the M33 is actively holding this RESMGR_RTC_INIT_RSC lock, I execute the following command from the Linux shell on the A35 core:hwclock --set --date="2026-07-18 12:34:56" --utcTo my surprise, the time is successfully changed.My question is: why does this happen? Does the OpenSTLinux RTC driver (rtc-stm32.c) completely bypass the RIF synchronization mechanism and force its

I have a working RLT8211F at my STM32MP257F board.I wonder why only the hardware reset is working PYRSTB (pin 12), but the software reset won't work?Should they not do the exactly the same thing?My Ethernet PHY is working, but it seems it requires as hardware reset GPIO from the MPU.I have tried to modify the code in realtek.c and phy_device.c by adding the function genphy_soft_reset to the struct in realtek.c. }, {  PHY_ID_MATCH_EXACT(0x001cc916),  .name = "RTL8211F Gigabit Ethernet",  .probe = rtl8211f_probe,                .soft_reset = genphy_soft_reset, /* <------- this */  .config_init = &rtl8211f_config_init,  .read_status = rtlgen_read_status,  .config_intr = &rtl8211f_config_intr,  .handle_interrupt = rtl8211f_handle_interrupt,  .set_wol = rtl8211f_set_wol,  .get_wol = rtl8211f_get_wol,  .suspend = rtl8211f_suspend,  .resume = rtl8211f_resume,  .read_page = rtl821x_read_page,  .write_page = rtl821x_write_page,  .flags = PHY_ALWAYS_CALL_SUSPEND,  .led_hw_is_supported

Hello,We are designing a custom board using the STM32MP157FAC1 and have used the STPMIC1APQR PMIC to power the microprocessor, similar to the STM32MP157F-DK2 evaluation board.We need to provide a Power LED on the front panel of the card to indicate that all the power rails generated by the STPMIC1APQR are operating correctly.Since the STPMIC1APQR does not provide a dedicated Power_Good (PGOOD) output signal, we are considering using the RSTn pin (Pin 1) to drive the Power LED along with its connection with NRST pin of STM32MP157FAC1. Our understanding is that RSTn is released (driven high) only after the power-up sequence has completed successfully and all required power rails are within specification. If any monitored power rail fails, RSTn would be asserted low.We plan to use a transistor stage to drive the LED from the **RSTn** signal so that:(1.) RSTn = High: Power LED ON(2.) RSTn = Low: Power LED OFFCould you please confirm whether this is approach is okay or not ? If not, kindly

I  have already submitted the case in ST Online Support, but have had no reply for over two weeks.

Hello,I’m using an Karo SOM module (MP257) on a custom board with SFP module.The SFP module is powered with the main 3.3V regulator. It has a TX_DISABLE input (0=ON, 1=OFF). This input :Is TTL Has an internal pull-up R (around 10k) Has an external pull-down R (10k) In connected to PE2This makes a voltage divider : without driving the TX_DISABLE line, the voltage is something like 3.3V / 2 (1.8V to be precise)Some simple tests to confirm that :SFP module unplugged => voltage is driven only by the pull down R => 0V A source meter on the TX_DISABLE confirms the presence and value of the internal RPU. Now let’s play with the MP2. Is this processor able to blink a led ? Don’t laugh, nothing could be further from the truth. After linux boot : gpioinfo shows PE2 is input. It should logically be driven by the driver, but for an obscure reason, this is not the case. At least we can do things manually… Set it to 0 ?gpioset -b disabled -d push-pull PE2=0=> Voltage is still 1.8V Ok, bad.

Hello,In the reference schematic of the STM32MP157F-DK2, the HSE clock is generated using the NDK NZ2016SH 24 MHz END4869F oscillator. However, this part is not readily available, and we are therefore looking for a suitable alternative.Could you please confirm whether the Abracon’s part ASE-24.000MHZ-LR-T can be used as a replacement to provide the HSE clock for the STM32MP157FAC1 device ? If this part is not recommended, kindly suggest a suitable alternative that is compatible with the STM32MP157FAC1.Regards

Hello,We are designing a custom board using the STM32MP157FAC1 device. In our design, we are not using the DSI interface or the ADC peripheral.We would like your guidance on the recommended handling of the corresponding unused pins.(1.) DSI Interface:Since the DSI interface is not used, how should the following differential signals be terminated ?(a.) DSI_CKP / DSI_CKN(b.) DSI_D0P / DSI_D0N(c.) DSI_D1P / DSI_D1N(2.) Analog Inputs:As the ADC is not being used, what is the recommended way to connect or terminate the ANA0 and ANA1 pins ?Could you please advise the recommended hardware implementation for these unused pins?Regards,

I have a custom design with STM32mp135f + MT41K256M16TW-107 DDR3L @ 533MHz that I want to bring up. I built a Linux image based on OpenSTLinux guides and it boots until my kernel is loaded (uboot logs : “starting kernel”) then its crashes without any logs even with earlycon. By testing the DDR with ST DDR Tool, I realized that byte-masked writes fail (test 9), but halfword & RMW32 work.  I noticed the byte lane swap but it is identical on the dk board. I am a bit lost and don’t know if the issue is timing/config related or due to my hardware design.  

Hello,We are designing a custom board using the STM32MP157FAC1 device. For programming and debugging, we are providing an STDC14 connector on our board and use the STLINK-V3SET debugger/programmer.As per AN5031 (Section 8.3.3), the recommended ESD protection device is ESDALC6V1W5. Snapshot is attached for kind reference.We have the following queries:Query 1:Can we use the HSP053-4M5 device instead of the ESDALC6V1W5 for ESD protection? We are already using the HSP053-4M5 to protect the data, clock, and command lines of the microSD card interface. Using the same device for the STDC14 interface would help us optimize the BOM.Query 2:Can we connect USART1_TX (PA9) and USART1_RX (PB15) of the STM32MP157FAC1 to Pin 14 (T_VCP_TX) and Pin 13 (T_VCP_RX), respectively, on the STDC14 connector for the STLINK-V3SET Virtual COM Port interface? Regards,PS  

I have a custom board using STM32MP131D integrated with ethernet PHY TI DP83867CR. I am using RGMII interface with a Magjack RJ45.I have been benchmarking the ethernet performance at 100Mbps using iperf3 with the custom board as the iperf client and my Linux test PC as the iperf server.When I run iperf in client mode on the custom board (DUT) in TCP, I see really bad TX performance:root@stm32mp131-sga:~# iperf3 -c 10.10.14.200Connecting to host 10.10.14.200, port 5201[ 5] local 10.10.14.102 port 35028 connected to 10.10.14.200 port 5201[ ID] Interval Transfer Bitrate Retr Cwnd[ 5] 0.00-1.00 sec 0.00 Bytes 0.00 bits/sec 3 1.41 KBytes[ 5] 1.00-2.00 sec 0.00 Bytes 0.00 bits/sec 2 1.41 KBytes[ 5] 2.00-3.00 sec 0.00 Bytes 0.00 bits/sec 1 1.41 KBytes[ 5] 3.00-4.00 sec 0.00 Bytes 0.00 bits/sec 1 1.41 KBytes[ 5] 4.00-5.00 sec 0.00 Bytes 0.00 bits/sec 1 1.41 KBytes[ 5] 5.00-6.00 sec 0.00 Bytes 0.00 bits/s

Both Micron and Samsung are putting LPDDR4 memories to EOF.What is the guaranty that STM32MP2 can support other affordable memories e.g LPDDR5?

I’m looking for a replacement of MT53E1G32D2FW-046 WT:C because it’s out of stock.So, I have found Samsung K4FBE3D4HM-TFCL LPDD4. From what I can see, it’s compatible with MT53E1G32D2FW-046 WT:C:Same voltage Same package Same pinout Single rank Follows JEDEC standardAre there anything else I need to know before making an order of that LPDDR4 memory?