Dual synchronous DMA stream for timer 1 PWM preriod and duty cycle management?

baptor · ‎2019-01-18

Hello everybody,

Here is my need

I am using STM32F469NI, and I need to generate a PWM signal using timer1.

I need to generate a burst of 4 pwm cycles. Each cycle must have a specific duty cycle value.

I already did that using DMA that load each duty cycles value to CCR register :

Now I would like to be able to do the same but to manage the period of each pwm cycles in a burst. ( ARR registrer ).

My gess is : can we make a dual DMA stream ( to ARR for period and to CCR for duty cycle) to be able to tune period and duty on the 4 pwm in burst?

I hope I am clear enought.

I attached my project.

Thanks in advance.

Baptiste

baptor · ‎2019-01-18

Here is the scope image of what I have as output.

waclawek.jan · ‎2019-01-18

Perform the DMA through TIMx_DMAR with TIMx_DCR set to 2 transfers starting at ARR. Have the ARR+CCR1 couples after each other in the DMA source array.

JW

baptor · ‎2019-01-18

Thanks a lot for your fast answer.

I see and ubderstand the overall principle but my level of confidence in coding is not good enought to do so.

May I ask a piece of code or link to stm32 example code that is using this configuration if you have?

Thanks you

Baptiste

waclawek.jan · ‎2019-01-20

http://www.efton.sk/STM32/tim_dcr_dmar.zip for DISCO-L4 (needs http://www.efton.sk/STM32/stm32l476xx.zip ). For the demo I deliberately used slow system clock (default) and a big prescaler, so that the result is visible https://community.st.com/s/contentdocument/0690X000006DAGGQA4 - a sequence of 12ms pulse in 30ms period; 2ms pulse in 30ms period; 50ms pulse in 60ms period; 20ms pulse in 100ms period - and repeat. The timers are basically the same across all STM32, so after adjusting the DMA-init piece this should run on your 'F4.

JW

baptor · ‎2019-01-23

Thanks a lot, I got this feature working. The code you provided helped a lot. For those who would like to implement the same feature :

For the timer 1, ( Ch2 and CH3 ) I had to use DMA2 channel 6 stream 5 that is targeting TIM1_UP.

using the function :

DMABurst_WriteStart(&TimHandle, TIM_DMABASE_ARR,(uint32_t*)aSRC_Buffer, TIM_DMABURSTLENGTH_5TRANSFERS);

I set the dma to write bursts of 5 elements from the ARR register to CCR3.

ARR register is managing PWM period, CCR2 is duty cycle on CH2, CCR3 is duty cycle on CH3.

At update, the DMA is loading one "line" of aSRC_Buffer in ARR RCR CCR1 CCR2 CCR3 registers.

/* Capture Compare buffer */ //ARR RCR CCR1 CCR2 CCR3

uint32_t aSRC_Buffer[aSRC_Buffer_ELEMENTS] = {

520, 0x0000, 0x0000,180,0x0000,

521, 0x0000, 0x0000,180,0x0000,

520, 0x0000, 0x0000,180,0x0000,

520, 0x0000, 0x0000,0x0000,180,

//0x0FFF, 0x0001, 0x00FF

};

I now able to manage duty cycle and period of PWM at each cycle.