STM32F407 with a 50.0MHz Oscillator

[Evelyn Sabbag]

Posted on March 20, 2018 at 19:00

I am running an STM32F407 with an ECS-2033-500BN Oscillator (50.0MHz) to accommodate the MCU and the ETH off the same oscillator. The circuit uses a fanout buffer to distribute the clock. Nowhere can I find information on how to configure the STM32F4 system clock with this high of a value (I assume there's a divide by 2 enabled in the bowels of the MCU) and the Clock Configuration tool doesn't help. Any suggestions? And yes, I've looked through the forum and the datasheet and I haven't been able to get the circuit to run.

I know the circuit works because previous FW was developed using NuTTx. I am porting the code to IAR and am stuck at the PLL initialization in the generated file system_stm32f4xx.c at the line: 

/* Wait till the main PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0) { }

Any help would be greatly appreciated.

 

[Jan Waclawek]

Posted on March 21, 2018 at 08:13

With external clock source you should set HSE to BYPASS.

To which pin is the clock connected?

You can check it with outputting HSE to MCO pin.

JW

[AvaTar]

Posted on March 21, 2018 at 08:49

50 MHz seems a bit high  - officially (DS) only quartz frequencies from 4.0 MHz to 24.0 MHz are supported.

[henry.dick]

Posted on March 21, 2018 at 13:13

'

Nowhere can I find information on how to configure the STM32F4 system clock with this high of a value...'

you mean the datasheet says nothing about that? seems to be a major flaw,

[Andrew Neil]

Posted on March 21, 2018 at 13:33

Actually 50MHz is allowed - it is the max:

http://www.st.com/content/ccc/resource/technical/document/datasheet/ef/92/76/6d/bb/c2/4f/f7/DM00037051.pdf/files/DM00037051.pdf/jcr:content/translations/en.DM00037051.pdf

 

[Andrew Neil]

Posted on March 21, 2018 at 13:38

http://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf

 

[Evelyn Sabbag]

Posted on March 21, 2018 at 14:04

Yes, AvaTar, that's what tripped me up as well. Also, the Clock Configuration tool does not allow 50 MHz.

[Evelyn Sabbag]

Posted on March 21, 2018 at 14:15

Thank you, Andrew, for the reply. The datasheet, DM00037051.pdf, mentions the 50 MHz OSC in Figure 98, but doesn't really provide any more information. The reference manual, en.DM00031020.pdf, is what I was missing. However, other than the bypass, it doesn't provide the same level of detail as the Clock Configuration tool. 

Once the bypass is selected and HSE is on, how does the /2 get selected? From the block diagram, either /2 or /20 is possible. And, once this is setup, can the HSE be treated as 25MHz in order to set the other parameters? I.e. PLL_N, PLL_Q, PLL_M, etc?

Thank you for all the help.

[AvaTar]

Posted on March 21, 2018 at 14:35

I didn't check the datasheet in detail, just relied on the 'front page information' - my bad ...

Also, the Clock Configuration tool does not allow 50 MHz.

Guess you mean the Excel tool, never used it myself.

I either used the output of this tool, delivered with the (SPL) project directly, or adjusted the clk configuration code (clk source, frequency and especially PLL multipliers).

The emitted source code (system_stm32f40x.c and *.h) had pretty decent comments, never had to consult the RM.

[Andrew Neil]

Posted on March 21, 2018 at 14:46

ST - like many (most?) others - split the description of their products across two documents:

1. The Datasheet - covers physical parameters; electrical, timing, mechanical specifications, etc 
2. The Reference Manual - covers operation of the various parts, registers, etc