STM32F407 SDIO CLK line is running below 400 kHz

[PChao.2]

Hello,

    I have a really strange problem with our STMF407 custom board that connects to a full-size SD Card socket using SDIO.  The MCU uses HSE at 8MHz and SDIO configuration as a 4-bit wide bus and div factor = 0.  All the other values are SDIO default.   We made several hundreds of this board, most of which have worked fine for several years.  It's been four years, and several boards have issues recognizing SD cards.  I checked several of them, and the SDIO CLK line during initialization is reading at 138 kHz with a 50% duty cycle.  The working one is running at 400 kHz; I think that's the lowest frequency SDIO should be running.  The slow rate was chosen to minimize power consumption.  In any case, I don't understand how it could be clocked at a much lower speed.
 
     The SDIO lines are series terminated with 22-ohm resistors, and each of them is pulled high with 4.7k resistors.. The signal edges look pretty clean when checked with an oscilloscope.  The MCU can be correctly read and write using STM32Programmer via the SWD interface.  The firmware is identical between the bad ones and the working ones.  A couple of things I have already done trying to figure out the issue:

-Reflashed the firmware.
-Tried different SD cards with different formats (FAT32, exFAT).  Cards work on the good boards but never work on the bad boards.
-Checked that all the pins from the SD card socket have connectivity
-Checked all the SDIO lines to have connectivity
-Replaced the series termination resistor.
-Replaced the pull-up resistors
-Replace the 8MHz oscillator with a new one.
-Replace both of the loading capacitors.
I use a logic analyzer to look at all the Lines: CMD, CLK, D0, D1, D2, D3, CardDetect(CD)

As far as I can tell, there's no apparent physical damage to the "bad" boards.  The only obvious change is the SDIO CLK line seems to not be correct.  On some boards, the CLK seems to be correct, but as soon as CMD is sent, all the data lines are active from 10-20 ms, and then all just stop. 

At this point, I'm running out of ideas.  I haven't tried just replacing the MCU, but that would be pointless since the MCU is the most expensive part on the board anyway.  It would be easier to scrap the board.  I'm just worried that this issue is related to the age of the STM32F407 (which supposedly has seven years guarantee).  Does anyone have any issues like this or a similar situation where the Sysclk is wacky?

[Tesla DeLorean]

Make sure the clock and PLL are actually starting.That HSE_VALUE is correct. Check frequency via PA8 / MCO pin.

The SDIO CLK needs to come from the 48 MHz PLL tap, normally used for USB / CRYP. Decompose and print of the clocking values for the MCU, PLL, AHB, APB, etc from the internal register settings.

Unpack the SDIO settings, instrument startup code. The initial probe of the SD Card will be done at a lower speed, if successful it will go to higher speeds, and wider bit widths.

[RhSilicon]

It's not the first time I've seen someone saying they're trying to use less than 40MHz on the F4. Could it be that users are not using the Clock Configuration tab of the IDE, more precisely the "Resolve Clock Issues" button?