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Subject: STM32N657X0H3Q Power Sequence Deviation – Impact on Reliability and OperationHello,I am designing a custom board based on the STM32N657X0H3Q, using the STM32N6570-DK as a reference. The MCU is configured to use the internal SMPS for VCORE generation.Unfortunately, my design does not fully comply with the recommended power sequencing described in the documentation:The various 1.8 V rails are generated from a single DC/DC converter. VDDA18USB, VDDA18CSI, and VDDA18ADC are powered directly from this 1.8 V rail. These rails are not gated by PWR_ON and therefore may become valid before or simultaneously with the PWR_ON assertion.The MCU appears to boot and operate correctly during initial testing, but I would like to understand the implications of this deviation from the recommended power sequence.My questions are:Does powering VDDA18USB, VDDA18CSI, and VDDA18ADC before (or independently of) PWR_ON create any risk of device damage or reduced reliability? Are there any known functio

Hello,I tried to get the HP properly working for hours now, but I get zeros on all axes every third output.What ist wrong? I tried a lot of different setup variation buts always with similar result.When disabling FDS (HP function), there are no zeros in the data stream.In this example I shaked the sensor.##########################WHO_AM_I: 0x33LIS3DH found.--- Register-Verification ---TEMP_CFG (0x1F) = 0x00CTRL_REG1 (0x20) = 0x2FCTRL_REG2 (0x21) = 0x08CTRL_REG3 (0x22) = 0x00CTRL_REG4 (0x23) = 0x80CTRL_REG5 (0x24) = 0x00CTRL_REG6 (0x25) = 0x00REFERENCE (0x26) = 0x00FIFO_CTRL (0x2E) = 0x00INT1_CFG (0x30) = 0x00INT1_THS (0x32) = 0x00INT1_DUR (0x33) = 0x00INT2_CFG (0x34) = 0x00INT2_THS (0x36) = 0x00INT2_DUR (0x37) = 0x00CLICK_CFG (0x38) = 0x00CLICK_THS (0x3A) = 0x00TIME_LIMIT (0x3B) = 0x00TIME_LAT (0x3C) = 0x00TIME_WIN (0x3D) = 0x00ACT_THS (0x3E) = 0x00ACT_DUR (0x3F) = 0x00--- Configuration finished --- ms; X; Y; Z;INT1 56; 184; 1

After weeks of debugging TXERR on USB host, I figured out that changing OTG clock from PLL3Q to HSI48 errors disappear.STM32H733 running at 336MHz from HSE @25MHz. USB connected to an LTE modem (CDC ECM). With few tasks and interrupts errors occur at an average rate of 1/minute, but under heavy load (30+ tasks and 5 TIM interrupts <1ms) the error rate rises to 20/minute ca.As said, using HSI48 errors completely disappear under any condition. Is HSI48 more stable than PLL? How does CPU load influence PLL? Alessandro

I'm trying to figure out which clock source the STM32L412 ADC uses in synchronous mode. The documentation doesn't seem to be consistent.Most diagrams show SYSCLK, while the text says HCLK (AHB clock).It looks to me like RM0394 Figure 13 and DS12469 Figure 5 are incomplete because they don't show the AHB bus as an ADC clock input. Am I missing something, or is this a documentation error?   

I'm working with an STM32F070 and trying to verify the Independent Watchdog (IWDG). My expectation is that if the watchdog is not refreshed, the MCU should perform a system reset after the timeout expires.The IWDG is configured as follows:MCU: STM32F070 Clock: HSI = ON (System Clock) LSI = ON (for IWDG) IWDG configuration: Prescaler = 256 Reload = 4095 Window = 4095 The watchdog is initialized using HAL_IWDG_Init().To force a timeout, I intentionally do not refresh the watchdog: // IWDG_KICK();while (1){ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, GPIO_PIN_RESET);}The full initialization is: hiwdg.Instance = IWDG;hiwdg.Init.Prescaler = IWDG_PRESCALER_256;hiwdg.Init.Reload = 4095;hiwdg.Init.Window = 4095;HAL_IWDG_Init(&hiwdg);According to the reference manual, with Prescaler = 256 and Reload = 4095, I expect a wat

I reviewed the code and found anti-windup is not implemented in the loop, is that correct?  Let me know if there is a version with anti-windup implemented, thank you.

Please tell me the model number of the QFN24L package IC marked "S2TX". 

Hi,I want to configure STM32L152RE board to max speed of 32MHz using HSE 8MHz. As per reference manual, flash latency can be configured only in 64 bit read operations. I want to use 32bit read operation for low power consumption. I am confused on how to use the board in bare metal programming specifically for flash latency part. I am using platform.io and want to initialize the RCC using HSE and PLL. I need guidance for RCC initialization and flash latency configuration portion.

In section 1.2 of DB5834Time-of-Flight (ToF) sensors software expansion for STM32Cube it is written that “The package is compatible with STM32CubeMX. It can be downloaded from and installed directly into STM32CubeMX, as described in UM1718”. I followed UM1718 but could not find “X-CUBE-53L9A1” in Tab “STMicroelectronics”. I’m using the CubeMX version 6.18.0. Also the upload of the zip-file via “From Local...” failed. The error message: “This file is eighter corrupted or not recogniced package. [...]”. How to proceed? Thanks for your help.

I have a very nice study using RTC smooth calibration, with the RTC steered by a GNSS receiver one second pulse and a software PI controller that redetermines the calibration every 32 seconds, kind of a PLL. I am using a STM32F746G Disco evaluation board for development. Phase comparison is by hardware (1 second RTC alarm output and 2 channel input capture on a 10 MHz timer).For optimizing the PI controller i would like deterministic results, but i don’t know what happens when i set a new smooth calibration value during an ongoing 32 second period.Does that initiate a new 32 second RTC smooth calibration period with the requested number of adjustments?Is a certain one of the 32 seconds better for setting the new calibration value? Which one?I  could analyze the 32 phase measurements in my PI controller time interval to see how many calibration steps actually happened, but maybe there are some simple rules.

I am using the STM32WBA55C 48-pin package, and TSC Group 4 cannot be set as a sampling capacitor. Does this mean I cannot use TSC in Group 4? I plan to use 12 TSC channels, 1 SPI channel, and 1 ADC channel, so please give me some advice.

I'm working on a completely bare-metal STM32L476RG project using GCC + CMake + OpenOCD + GDB (no HAL, no CubeMX).The MCU consistently HardFaults immediately after entering Reset_Handler, before any .data copy or .bss initialization occurs.ToolchainMCU: STM32L476RG GCC: arm-none-eabi-gcc 15.2.1 OpenOCD + GDB CMake project -mcpu=cortex-m4 -mthumb -nostartfiles LinkerMemory layout:FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024KRAM (rwx): ORIGIN = 0x20000000, LENGTH = 128K_estack = ORIGIN(RAM) + LENGTH(RAM);Relevant symbols:_sdata = 0x20000000_edata = 0x20000030_sidata = 0x08000A7C_sbss = 0x20000030_ebss = 0x20000034 Vector tableVector table begins at 0x08000000.First entries:0x20020000 // MSP0x08000197 // Reset_Handler0x08000201 // NMI0x0800018D // HardFaultReading both0x00000000and0x08000000shows identical contents, so the Flash alias appears correct.VTOR:0xE000ED08 = 0x00000000 Reset_Handlervoid Reset_Handler(void){ extern uint32_t _sdata, _edata, _sidata; extern

Hello, I created a project (BLE_p2pServer) in STM32CubeMX (6.18.0), but it won't build.Unlike other projects, this project has a folder-like icon in the Project Explorer.I created the project using the same procedure as other projects (BLE_TransparentMode, etc.), so do you know why this is happening?Deleting and recreating the project doesn't change the situation. 

I programmed BLE_TransparentMode to perform RF testing on a custom board equipped with an STM32WBA23.I want to transmit unmodulated CW, but I can't find a way to do this using HCI commands.Is there a vendor-specific command to achieve this? Alternatively, methods such as calling an API or modifying registers would also be acceptable.

Hi,I have a system with 11 STM32 in a single JTAG chain. I’m trying to debug device with JTAG address 10,45 (JTAG device position 10, IR -pre-length of 45) and I’m getting this error message when running my launch configuration:This is my entry in launch.json, my probe is a J-link:{            "type": "jlinkgdbtarget",            "request": "launch",            "name": "JTAG Launch Dev 10",            "origin": "snippet",            "cwd": "${workspaceFolder}",            "preBuild": "${command:st-stm32-ide-debug-launch.build}",            "runEntry": "main",            "serverInterface": "JTAG",            "serverJtagCfg": "45,10",            "imagesAndSymbols": [                {                    "imageFileName": "${command:st-stm32-ide-debug-launch.get-projects-binary-from-context1}"                }                            ]        }, Debugging device 0,0 on the same chain works (has similar firmware written on STM32Cube extension for VSCode) from STM32CubeIDE extension for VS

I would like to implement a  secure firmware update solution that will work in both an STM32G4A1 and an STM32U0 83.  Different applications, but I would like to use the same basic bootloader and PC update application.  Both would updated over USB.  They have basically the same security features and both have the AES-GCM accelerators.I've been watching the MOOC - Security series to learn how to do this.  I got to the end of  "Security Part4 - STM32 security in practice - 15 Secure firmware update" and had some questions since there isn't any lab video for this module like there are for the modules that came before it. I've also looked at the Silicon Labs AN0060: Bootloader with AES Encryption app note, which is similar in implementation to what I am thinking of doing. The link for the slides for the MOOK module is at the bottom of this page:https://www.st.com/content/st_com/en/support/learning/stm32-education/stm32-moocs/STM32_secur

Hi Community, We are exploring the migration of our FreeRTOS-based firmware to Zephyr. Our current design heavily relies on TouchGFX (provided by ST) for controlling an 800×480 touch display. Here are some key details of our setup: TouchGFX with external SDRAM for a double frame buffer using the FMC peripheral Images, fonts, and text stored in external QSPI Flash LTDC controller in use DMA2D accelerator enabled RGB image compression utilized Is there any sample application or detailed documentation available for achieving this on Zephyr? I have already briefly reviewed the following resources: Abstraction Layer Architecture | TouchGFX Documentation and https://support.touchgfx.com/docs/basic-concepts/operating-system#touchgfx-os-wrappers However, I need more guidance, specifically: Examples or reference projects for TouchGFX on Zephyr Detailed documentation on integration steps We have a tig

I’m having an issue with throughput on the STLINK-V3MODS VCP when used with the second BRIDGE UART.  If I set both the VCP and 2nd VCP for 115200 baud, I am only able to simultaneously send 5.76 KiB/s through each (half throughput).  If I use only the VCP at 115200, I’m able to send 11.52 KiB/s (full throughput).I saw no mention of any such limitation in the documentation.  Am I doing something wrong?STLINK-V3MODS firmware 3.17.11Windows 11 version 25H2 (OS Build 26200.8875) 

Hi, everyone,I'm trying to implement USB CDC on an STM32H5E5 board using the classic USB device middleware. I followed another community thread that provides the steps to do this: How to Use STMicroelectronics’ Classic USB Device Middleware with the New STM32 Families:  When compiling the code, I encountered some errors at this point in the library: USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev){pdev->pData = &hpcd_USB_DRD_FS; HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x40);HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x80);HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , CDC_IN_EP , PCD_SNG_BUF, 0xC0);HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , CDC_OUT_EP , PCD_SNG_BUF, 0x100);HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , CDC_CMD_EP , PCD_SNG_BUF, 0x140); return USBD_OK;}The error messages are as follows Description    Resource    Path    Location    Type'PCD_SNG_BUF' u

The new version of CubeIDE is truly terrible.With a new project, there's no way to tell if it was created via the IDE or MX.On top of that, they don't synchronize with each other—an issue that never occurred with the unified versions up to 1.19.

Hi ST Community,I am currently working on an analog sensor acquisition project using the NUCLEO-N657X0-Q (STM32N657X0) board on STM32CubeIDE (version 1.19.0). I am attempting to read a Keyes pressure sensor via ADC1 on PA1 (ADC1_INP1).Physical Wiring & Setup Sensor Connections: The pressure sensor is physically wired to: VCC -> Board 3.3V GND -> Board GND Signal Out -> PA1 (bridged with a 1/2 resistor divider to ground to ensure the voltage never exceeds 1.8V). CN12 Jumpers Connected: Pin 13 / Pin 14 (VDDA1V8) is connected with a jumper cap to supply 1.8V to VDDA. Pin 11 / Pin 12 (VDDIO) is connected with a jumper cap.  STM32CubeMX Configurations VREFBUF: Configured as Disable (since the NUCLEO board provides an external 1.8V reference to VREF+). Security & RIF (RIFSC Panel): ADC1: Configured as Non-Secure, Unprivileged (unchecked), Unlock (unchecked), and assigned to the Application context. GPIOA: Configured as Non-Secure, Unprivileg

There seems to be a documentation error between DS14053 Rev 4 and RM0492 Rev 3.  In the data sheet, section 3.17, table 3, "ADC Features" we see a different set of features compared to the reference manual, section 19.3, table 107.  The data sheet claims oversampling up to x1024, a data register of 32 bits and gain compensation is supported.  The reference manual claims oversampling up to x256, a data register of 16 bits and no gain compensation.The register set description only has oversampling fields with values up to 256.  It would be helpful if ST could correct whichever document is wrong, and if the reference manual is wrong and oversampling up to x1024 is supported, then please also correct the register definitions.Thanks,TG

I have two STM32G474 on a custom PCB, in which I want to use a SOM to program the microcontrollers via UART (USART1 or USART2).While most PCBs work fine (toggle BOOT0 + NRST and program via UART), some PCBs have intermittent access on the UART. It is not always the same microcontroller that fails on the boards.Tests I have done:Programming via USB DFU always works, even when toggling BOOT0 and NRST with the SOM, so it seems it is going into bootloader mode correctly. In the SOM I am using stm32flash. I have checked that no other signals are triggering the bootloader on another interface (e.g. I2C, other USART). I have checked that the 0x7F command is being sent correctly (timing, clean edges, amplitude) There is no reply at all from the micro I have tested with pull-ups and/or series resistors on RX line and better decoupling on power supply, nothing made a difference The same UART lines work fine during runtime, they only fail when in bootloader mode The good PCBs are always good and

I am trying the NUCLEO545RE-Q. I created a project, imported it to STM32CubeIDE 2.2.0. The build button is grayed out. I found several videos for version 2.0.0 where is easy and straight forward. With this version is not and I couldn’t find any help. What am I doing wrong? 

Hi everyone,I'm planning to develop a VoIP/IP intercom application using FreeRTOS, LwIP, SIP, RTP, UDP/TCP, and an audio codec (SAI/I2S). I'm trying to decide between the STM32F7 and STM32H7 series (e.g., STM32F769I-DISCO vs STM32H750B-DK).From real-world experience, what are the main differences between the F7 and H7 beyond the datasheet specifications? Is the H7 worth choosing for a new networking/audio project, or is the F7 sufficient? Are there any practical drawbacks of the H7, such as cache or DMA complexity?I'd appreciate any recommendations or experiences from developers who have worked with both series.