Load Pull for RF PA for STM32WL series Low band version.

[msharfi]

I am designing a custom board using the STM32WL55 in UFBGA73, operating at 433 MHz, and I am currently facing higher-than-expected TX current consumption together with lower RF output power.

I would like to know whether ST can provide load-pull data, optimum complex load impedance, or PA matching information at 433 MHz, particularly for approximately 0 dBm and +14 dBm TX power.

I have compared my custom board against an STM32WL Nucleo board using the same firmware and RF settings.

My measurements so far are:

Nucleo board TX current: approximately 65.8 mA
Custom board TX current: approximately 72 mA
Difference: approximately 6–7 mA higher on my custom board
Conducted RF power measurement on my custom board indicates approximately 10 dB lower output power than expected

My next step is to measure the impedance presented to the PA at the beginning of the RF matching network and determine whether the PA is seeing the correct load at 433 MHz.

Ideally, I would like to compare my measured impedance with the optimum PA load impedance from ST load-pull characterization.

I am particularly interested in the optimum load for:

433 MHz
0 dBm TX power, where my priority is minimum current consumption / maximum efficiency
+14 dBm TX power, where my priority is maximum output power with reasonable efficiency
Any intermediate power level if the optimum impedance changes significantly with output power

One reason I am unsure whether this is purely a matching issue is the TX current consumption I measure on the Nucleo board itself. Based on the STM32WL55 datasheet, I understand that TX current can be around 40 mA under 1.8 supply voltage / 14dbm power conditions, whereas I am measuring approximately 65.8 mA on the Nucleo board and approximately 72 mA on my custom board.

Could you please clarify:

Is load-pull data or optimum PA load impedance versus frequency/power available for the STM32WL55 at 433 MHz?

What complex impedance should the PA ideally see at 433 MHz for approximately 0 dBm and +14 dBm?

Are the reference matching values used on the Nucleo board optimized primarily for maximum output power, efficiency, or 50 Ω output matching?

What exact test conditions should be used when comparing TX current against the datasheet values — supply voltage, PA path, modulation, frequency, regulator mode, etc.?

Could a significant mismatch at the PA output explain both a roughly 10 dB reduction in conducted RF power and the additional TX current consumption I am seeing?

edit: I have checked application note AN5457 and all of the PA or TX load pull and impedance measurements are for High band version of the Chip.

[Ronan T.]

Hi,

We have some load pull data when using BGA package at 470MHz.

Optimum impedance to be seen by the PA is then 20+j30 for +17dBm operation and 18+j22 for 20dBm operation at this 470MHz frequency. Slight retuning

In terms of output power, are you using the IPD (BALFLB-WL-07D3) or did you go for a discrete SMD solution (like our reference design STDES-WL5U4SBB) for the RF front-end ? FYI, the IPD is specified for 470MHz and upwards, RF performances degradation is therefore expected at 433MHz

The RF Bill of Material on our Nucleo board is optimized for both RF performances and current consumption. 

Have you measured the total current on the board or did you monitor the VddRF node (see datasheet figure 15)

Also, the PA parameters play a very important role in current consumption (see AN5457, table 2)

Nevertheless, there is no reason why you shouldn’t get the datasheet values on your own PCB. 

 

==> I suggest that you enter an OLS ticket so that we can continue investigating your point (to make a schematics & layout of your PCB too) 

 

Rgds

ronan

 

 

[msharfi]

Case Number: 00268004

 

Thanks for the suggestion i have opened an OLS ticket. 
The current has been measured from the VDD pin from the stm32 using NRF board. 
The impedance i want is for the PA LP pin operating at 0dbm and 14dbm for lowest current consumption. 

IF the RF nucleo board is optimized for low current then its not a matching problem i believe? firmware configuration is similar to both nucleo board and my board and both shows high current consumption compared to the datasheet

[msharfi]

apparently STM cant help and continue with the support until i provide a  production forecast through ST SALE. 
So i will continue the case here.

Summary:

I'm facing two problems .

    High current consumption Myboard (65.4mA) Nucelo (72mA) instead of the 40mA the current has been measured from the VDD from the STM32 3.3V pin.
    Very low output power from the RF pin from my board (10db loss) 

What I plan doing next is . 
1. Current cons issue: 
A. Measure the Current in the VDD RF pin if low good if not 
B. Change PA config for the STM32 nucleo board to get low current consunption on 14dbm and 0dbm.
C. change PA matching
2. 10db Loss issue 
A. Measure my antenna impedance put it in Simulation software and see the impedance form the PA. 
B. Measure the Path loss  (S21) in the Board as well as the real impedance (S11) seeing by the PA.
Any suggestions or help would be great! 
1. for Changing PA matching i might need the optmized load pull for the PA at 433MHz for 0dbm 14dbm using the  BGA package