The reason why TIM14->CCR1 = 50 and TIM9->CCR2 = 49 coexist
The reason why TIM14->CCR1 = 50 and TIM9->CCR2 = 49 coexist
1. Background and Configuration
· Chip: STM32F407ZGTx
· Connection: TIM14_CH1 (PF9) outputs PWM, connected via jumper to TIM9_CH1 (PE5) for input capture
TIM14 (PWM output) configuration:
· Clock 50 MHz, prescaler 4999, counting frequency 10 kHz
· Up-counting mode, ARR = 199, CCR1 = 50
· PWM Mode 1, active high
TIM9 (input capture) configuration:
· Clock 50 MHz, prescaler 4999, counting frequency 10 kHz
· Slave mode: Reset mode, trigger source TI1FP1 (rising edge)
· CH1: rising edge direct capture (CCR1)
· CH2: falling edge indirect capture (CCR2)
2. Observed Phenomenon
In the capture interrupt, the following registers are read:
```c
uint16_t IC1_Width = __HAL_TIM_GET_COMPARE(&htim9, TIM_CHANNEL_1); // TIM9->CCR1
uint16_t IC2_Pulse = __HAL_TIM_GET_COMPARE(&htim9, TIM_CHANNEL_2); // TIM9->CCR2
uint16_t CCR = __HAL_TIM_GET_COMPARE(&htim14, TIM_CHANNEL_1); // TIM14->CCR1
```
LCD display results:
Register Value Meaning
TIM14->CCR1 50 PWM compare threshold set by user
TIM9->CCR1 199 Rising edge capture value (period)
TIM9->CCR2 49 Falling edge capture value (pulse width)
Core confusion: Why is TIM14's CCR1 50, while TIM9 captures the falling edge of the same PWM waveform and CCR2 is 49? The two differ by 1. Is this expected behavior of the STM32 timer? I asked an AI, and it told me: when the falling edge triggers, TIM9's CNT has not yet become 50, it is still 49.
So CCR2 = 49. The counter increment and the edge detection latching occur in the same clock cycle, but the latching action occurs before the counter increment. Inside the STM32 timer, when the counting clock edge arrives, the hardware first checks whether there is an input capture event (falling edge). If there is, it immediately latches the current CNT value (which is still the old value 49) into the CCR, and then the CNT performs the +1 operation to become 50.
Therefore, the falling edge latches the pre-increment value of 49. Is this statement correct?
