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Hi,I am using STM32H747I-DISCO with MB1166-A09 (NT35510) and Zephyr + LVGL with MIPI DSI Video Mode.I am facing a diagonal/slanted tearing line when the display is configured in landscape mode.Portrait mode: works correctly Landscape mode: diagonal/slanted tearing appears during screen updates Hardware: STM32H747I-DISCO + MB1166-A09 / NT35510 Software: Zephyr + LVGL PROI have found several related discussions about this issue, but I haven't found a clear solution for landscape DSI Video Mode.Is this a known limitation/issue with the display/DSI configuration? Is there a recommended solution for running this display reliably in landscape Video Mode?Any guidance from ST or anyone who has solved this would be greatly appreciated.

Hello everyone,I'm working on a custom PCB (professionally soldered, LGA packages) builtaround an STM32G474RET6, and I'm stuck on a communication issue with twoof my three SPI sensors. I'd really appreciate some insight from anyonewho has run into this before.My setup:- Host MCU: STM32G474RET6- Shared SPI3 bus: SCK=PC10, MISO=PC11, MOSI=PC12- TMAG5170 (SPI-only magnetometer), CS=PA11- ISM330DHCX (IMU), CS=PD2- MMC5983MA (magnetometer), CS=PA12The symptom I'm seeing:My TMAG5170 communicates perfectly over SPI, which tells me my SPI3 bus,my shared SCK/MISO/MOSI wiring, and my power rail are all healthy.However, my ISM330DHCX and MMC5983MA never respond in SPI mode — WHO_AM_I/ Product ID reads keep returning garbage (0xFF).Here's what I've already tried:1. I ruled out a software bug by switching from separate   HAL_SPI_Transmit / HAL_SPI_Receive calls to a single   HAL_SPI_TransmitReceive — no change.2. I checked for solder bridges under the LGA packages with a multimeter   (MISO to 3V3,

I’ve noticed that the order of the registers seems to matter. I would like an explanation as to why this is the case and if there is anything documented on this front.Specifically if you want to request the following registers: 25, 89, 1425, 2649, 7001, 73It appears that for some reason or another 73 must be last. If you request the above registers with 73 being anywhere but the last register it seems to cause the G4 to lock up and stop responding to any MCP or ASPEP commands. You also seem to be unable to recover without power cycling the core.Valid Order: 25, 89, 2649, 7001, 1425, 73->e9 00 00 b0->11 00 19 00 59 00 59 0a 59 1b 91 05 49 00<-4a 01 00 f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2e 00 00 00Invalid Order: 25, 89, 73, 2649, 7001, 1425->e9 00 00 b0->11 00 19 00 59 00 49 00 59 0a 59 1b 91 05No response and the G4 hangs...Somehow it seems that the ST Motor Pilot is aware of this as it does place all the STATE register last in the packet.Motor Pilot v6.4.

Hello,we’are using CubeIDE (1.19 so far) and STM32H750B-DK boards for our several University courses. We have quite big repositories with working projects (mostly based on CubeMX generated .ioc and code) that can be edited, regenerated, debugged flawlessly in 1.19.Is it possible to import those projects in V2 and regenerate code and .ioc files in new v2 environment as it was possible before?I’ve heard that users have problems with migration of these types of projects - is this true? If there are problems, what to do in this situation? Will this ever be solved? Thanks,regards,Robert.   

Hello I would like to build a full bridge converter according to attached topology picture. The signals for controlling the switches should be like in the picture pwm_scheme. The frequency should be 500KHz. How to configure TIM1 or TIM8 on STM32H725ZGT6 to achieve this? To control the current i1 with lowering the duty cycle of the PWM which input is better to use: ETR or BKIN? Best regards Simon

Hello all ! Has anyone heard of the LX32F072CBT6 microprocessor? I found it when looking for the hardware used by a client.AI says me:“The LX32F072CBT6 is an alternative part number or specific designation that corresponds directly to the STM32F072CBT6 microcontroller manufactured by STMicroelectronics.” It seems to be a chinese copy of the STM32F072CBT6 but has someone some info about it? Kind regards,Michaël

Reporting two issues when using STM32CubeMX v6.16.1 to generate STM32N6 code. I created new secure only template project for STM32N6570-DK to demonstrate the issue (it's attached).Only changes to the new project are these:In MMT defined RAM2 area over AXI SRAM3-6. Also check the "Apply Application Regions Settings to Peripherals".Then activated RIF for FSBL:Now generate code.It generates FSBL\Core\Src\main.c function SystemIsolation_Config(void).There are two function calls that cause assert failure because they violate the HW capability: /* set up base region configuration for CPUAXI_RAM0*/ /* region2 is secure */ risaf_base_config.EndAddress = 0x1003ff; risaf_base_config.StartAddress = 0x00000400; HAL_RIF_RISAF_ConfigBaseRegion(RISAF2, RISAF_REGION_2, &risaf_base_config); /* set up Sub region configuration for CPUAXI_RAM0*/ risaf_sub_config.EndAddress = 0xfffff; risaf_sub_config.StartAddress = 0x00000400; HAL_RIF_RISAF_ConfigSubRegion(RISAF2, RISAF_REGION_2, RISAF_S

The AN3156 explains on page 18 the Read Unprotect Command:This command is selected when wValue = 0 and the first byte of the buffer sent by the host is 0x92. The buffer length is only one (the command) byte.The host sends a DFU_DNLOAD request with the above parameters to remove the read protection of the internal flash memory.   It is very useful that you implemented a command to remove the read protection.But this is useless if there is also a write protection active.The user has no way to remove a write protection over the DFU protocol.Why does this command not remove both: The read protection AND the write protection at the same time?Why does STM implement nothing that allows to remove a write protection ?

Hello,I would like to confirm my interpretation of the marking M1013 on the old BUX10 transistors (TO-3 package) I’m using. I believe M stands for Malaysia and 1013 stands for week 10 of 2013 ; is this correct ?Thanks !

Does anybody know what the marking KCY547C means? Is it normal that there are several markings in one reel? 

I downloaded and installed stm cube programmer, but every time I try to open it, I immediately get an error message saying that it quit unexpectedly. Currently running mac high sierra 10.13.6. How can I fix this problem?

EnvironmentMCU: STM32H573 (custom board) STM32CubeProgrammer & STM32 Trusted Package Creator: v2.23.0 (same version) X-CUBE-RSSe: installed (RSSe SFI binary v3.1.0, RSS v2.2.0) License: ST HSM (hsm=1, slot=1) Boot: custom OEM bootloader (OEM-iRoT), not STiRoT / not mcuboot Connection: HotplugWhat I'm doing I'm evaluating SFI without Secure Manager, installing my own firmware into internal secure flash. TrustZone is enabled (TZEN=0xB4), and my final option bytes (CSV) set:BOOT_UBE = 0xB4 (OEM-iRoT) SECBOOTADD = 0xC0000 (0x0C000000) SECWM1 = 0x00–0x7F, SECWM2 = 0x00–0x7F (all secure)Memory layout (secure alias 0x0C000000):File Address Size 1.bin 0x0C000000 22.2 KB 2.bin  0x0C008000 ~813 KB total 3.bin 0x0C0F7FA0 80 B 4.bin 0x0C0F8000 32 B 5.bin 0x0C1F8000 5.6 KB Behavior The SFI process starts correctly:License processed OK Image header processed OK Area 1 (type H) processed OK Fails at Area 2 with:Error: Execution of RSS CMD failed, returned value = 0xF

New question split from this post.One additinal request: When checking if bootloader pin configuration has an impact on the real application it would be helpful to know the default level for output pins, likedoes the UART_TX pin drive active high or low?does the boot loader drive the SPI MISO output pin HI, LO or Z?is the CAN_TX pin drven HI or LOW?Thank you!

Dear we working on safety critical application on railway. We are going to workout a FMECA analysis on our solution and I need further documentation on the STM32WLE5. At the begininning of the project we already signed an NDA with STM to get safety plan for another STM MCU. May we talk directly than I will send you a copy of the NDA ? Thanks a lot  

In official schematic MB1248 Rev-04 on SDRAM page:SDNE Connected to MCU pin PH6,SDNWE to PH5,SDCKE to PH7,When I create prject using TouchGFX template and open .ioc file in CubeMX or open SDRAM driver in CubeIDE the pins are connected as follows:SDNE to PB6SDNWE to PC0SDCKE to PB5My question is which is correct: Schematic or Code/.ioc file? 

Hello Every One,Hardware / Software EnvironmentBoard: STM32MP257F-EV1Device: STM32MP257FAIxIDE: STM32CubeIDE v2.0.0 (Windows)Firmware package: STM32Cube FW_MP2 v1.2.0OpenSTLinux version: openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11What I DidFlashed OpenSTLinux image to eMMC using USB DFU with:FlashLayout_emmc_stm32mp257f-ev1-ca35tdcid-ostl-optee.tsvFlashing completed successfully.Linux boots correctly and I can log in via UART:root@stm32mp2:~#Created a simple GPIO project for Cortex-M33 using STM32CubeMX and STM32CubeIDE:Selected MCU: STM32MP257FAIx (not board)Selected “M33 Master”Toolchain: STM32CubeIDEProject builds successfully without errorsLinker Memory ConfigurationThe generated linker script places CM33 firmware in DDR memory:NS_VECTOR_TBL : ORIGIN = 0x80100000FLASH : ORIGIN = 0x80100600RAM : ORIGIN = 0x80A00000VIRTIO_SHMEM : ORIGIN = 0x812F8000IPC_SHMEM_1 : ORIGIN = 0x81200000So the CM33 firmware is located in DDR (0x80xxxxxx region).ProblemWhen attempting to debug or download

Dear ST-Community,I was able to run QNX8 on stm32mp257f-dk (see it here: https://github.com/KozhinovAlexander/qnx8-bsp-stm32mp257f-dk)I have following boot-stage setup:#Opt Id Name Type IP Offset Binary- 0x01 fsbl-boot Binary none 0x0 arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-programmer-usb.stm32- 0x02 fip-ddr FIP none 0x0 fip/fip-stm32mp257f-dk-ddr-opteemin-programmer-usb.bin- 0x03 fip-boot FIP none 0x0 fip/fip-stm32mp257f-dk-opteemin-programmer-usb.binP 0x04 fsbla1 Binary mmc0 0x00004400 arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-sdcard.stm32P 0x05 fsbla2 Binary mmc0 0x00044400 arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-sdcard.stm32PD 0x06 metadata1 FWU_MDATA mmc0 0x00084400 arm-trusted-firmware/metadata.binPD 0x07 metadata2 FWU_MDATA mmc0 0x000C4400 arm-trusted-firmware/metadata.binP 0x08 fip-a FIP mmc0 0x00104400 fip/fip-stm32mp257f-dk-opteemin-sdcard.binPED 0x09 fip-b FIP mmc0 0x00504400 nonePED 0x0A u-boot-env ENV mmc0 0x00904400 noneP 0x10 bootfs System mmc

Hello,I have generated a project with STM32CubeMX2 for NUCLEO-C5A3ZG. Now I made changes to the MX project and try to generate the project again. But during the generation a list pops up, that asks for overwrite approval. I can not interact with the list properly. (I can’t scroll and pressing ENTER does nothing)Is this a known error or is there a workaround?

 Hi,I am working with the STM32MP257F-EV1 board and would like to debug the Cortex-M33 core using the debugger using ST-LINK.Currently, I am unable to debug the Cortex-M33 core directly and I receive an error during the debug connection. I have attached a screenshot of the debug error for reference.I noticed the following behavior: If I boot the Cortex-A35 core from the SD card and allow Linux to complete its boot process, I can then successfully debug the Cortex-M33 core. However, if I do not boot Linux on the A35 core, I am unable to connect to/debug the M33 core. I would like to know whether the Cortex-M33 on the STM32MP257F-EV1 can be debugged standalone, without booting the Cortex-A35/Linux, similar to debugging the Cortex-M4/M7 on a conventional STM32 MCU such as the STM32H745XI-DISCO.Specifically: Is booting Linux on the Cortex-A35 mandatory before the Cortex-M33 can be debugged? Is there a way to debug the Cortex-M33 standalone immediately after reset/power-up, without boot

Hi all,I have this kit but I don’t have any bolts holding the display PCB to the main PCB. I tried to look at the BOM for a reference to the part number but I don’t see anything for the bolts. I took one of the bolts holding the standoffs to the main PCB and it looks like an M4mm x 0.5 but I rather be sure before I order a few online. I have enough stuff that doesn’t match them and I rather not add more :-).Thanks

hi We are using the STM32F103CBT6 as the ST-Link controller in our new gateway board.In the first version of the board, the ST-Link did not work as expected. We have made some changes, and this is the second version of the board.Could you please review the ST-Link schematic section and let us know if there are any issues or recommended changes? Your feedback would be very helpful in ensuring that the ST-Link works correctly in this version.Thank you in advance for your support.

Hi Team,good day,may we seek your expertise regarding these two PNs.L9369-TR and L9369S-TR.Does the "S" suffix indicate a newer, improved model?What specific design changes have been made?Is there any official documentation from the manufacturer for S?thank you very much.

Hi,I am configuring the STM32L412KB to operate as an SPI1 slave in 3-wire (1-line / half-duplex) mode.I have configured the following pins:PA4 → SPI1_NSS PA5 → SPI1_SCK PA6 → SPI1_MISO / SDIOWith this configuration, the SPI communication works correctly.However, in a previous support case with ST, I was advised to use PA7 as the SDIO pin. The information I received was:“On SPI1, the single data line in 1-LINE (half-duplex) mode is the MOSI pin = PA7.”According to the STM32L412KB datasheet, PA7 is indeed the SPI1_MOSI alternate-function pin, while PA6 is SPI1_MISO.However, when I configure PA7 as the SDIO line, the communication does not work. It works correctly only when I use PA6 as the SDIO line.Could someone clarify this behavior?In particular, I would like to understand whether, in SPI1 slave + 1-line (half-duplex) mode, the bidirectional data line is actually expected to be connected to PA7 (MOSI), or whether PA6 (MISO) can/should be used in slave mode.If there are any specific SP

I encountered a potential bug in CubeMXs Configuration Checks for USBX.I am trying to configure USBX in standalone mode. When i try to increase the value of “USBX System Stack Size” to be higher than 1024 i get a warning that it needs to be lower than the USBX memory pool size, even when this is the case.Attached is a screenshot with example settings. To reproduce the error set USBX System Stack Size to 1025.The used MCU is a STM32U385CGTxBest regards, Cecil  

Good afternoon,We are working with STM32H7A3 boards and are currently migrating our build and flashing toolchain from STM32CubeIDE 1.9.0 to 2.2.0. During the migration we ran into a flash programming failure that we have traced to the device description, and we would like your confirmation before we adopt a workaround.WHAT WE OBSERVEProgramming at 0x08100000 is rejected with "Operation exceeds memory limits" under 2.2.0. The same operation succeeded under 1.9.0.Investigating this led to two findings on Device ID 0x480:STM32_Prog_DB_0x480.xml declares the Bank 2 base address for the 1 MB configuration as 0x08080000, which contradicts RM0455 Rev 13, Table 15, and consequently excludes the documented Bank 2 base at 0x08100000 from the valid range; Writes to 0x08080000 are accepted and verify successfully on our samples, despite Table 15 listing that range as not mapped.FINDING 1 - DEVICE DESCRIPTION FILEThe file defines two configurations for Device ID 0x480, corresponding to the 2 MB and