Ethernet switch in STM32P257 DK BOARD

[M.MALLESH]

Hi all,

I am bringing up the Ethernet switch (ETHSW) on an STM32MP257F-DK, bare-metal on the Cortex-A35 (no OS), following RM0457 Rev 5.
Ping works with the switch bypassed (ETH1 directly to the PHY), and ping also works under Linux with the switch enabled on the same board. In bare-metal switch mode, ARP works but ICMP never arrives.

SETUP
- ETH1 -> Port0 (internal, no PHY), PHY (RTL8211F, RGMII) on Port2, negotiated 100 Mbps full duplex
- SYSCFG_ETHSWCR = 0x6 
  SYSCFG_ETH1CR = 0x12 
- Init order:
ETHSW reset -> clocks -> SYSCFG_ETHSWCR -> release reset -> pulse ETHSW_FES_GEN_CTRLR INIT_REQ (bit 15) -> then ETH1 clocks/reset/DMA
- PORT0 UNDER MANAGEMENT,MII,100 MBPS
- PORT2 UNDER NORMAL, MII,100 MPBS 

WHAT WORKS
- Broadcast/multicast from the PC reach ETH1 (ETH1 MMC broadcast counter increments)
- The board's ARP reply (unicast) leaves ETH1, crosses Port0 -> Port2 (Port0 RX_UNICAST=1, Port2 TX_UNICAST=1) [confirm in Wireshark that the PC actually receives it]
- Dynamic MAC table shows the PC MAC on port 2 and the board MAC on port 0
- VLAN table via ETHSW_FES_VLAN_CMDR: VLAN 0x000, 0x001, 0xFFF all have members = 0x7, tagging not disabled; FESx_VLAN0R = 0x8FFF on all ports

WHAT FAILS
- Port2 RX_UNICAST stays at 0 while RX_BROADCAST/RX_MULTICAST increment
- No ICMP echo request ever reaches ETH1 (unicast counter in ETH1 MMC = 0)
- The PC keeps sending ARP requests [confirm with "arp -a" / Wireshark]
- FES drop counters (FULL_DROP, Q_DROP, RX_POLICED, EARLY_DROP, RX_CRC_ERROR) all read 0

question

• When the FES ports are configured in HW_MODE_GMII, the FES RX/TX counter values do not increment even though Ethernet traffic is present and the PHY link is up. Why is this happening? Is there any additional clock, interface, or FES register configuration required for the counters to operate correctly in GMII mode?
• When the FES ports are configured in HW_MODE_MII, the FES RX/TX counters increment correctly, but unicast ICMP/ping traffic does not reach ETH1/CPU. Broadcast and multicast traffic are received successfully. What additional FES configuration is required for unicast forwarding in MII mode?

 

[M.MALLESH]

CORRECTION / MORE DETAILS

Setup: STM32MP257F-DK, bare-metal A35, RM0457 Rev 5, 100 Mbps.
Port0 = ETH1 (Management mode, MII, 100M). Port2 = RTL8211F (Normal mode, MII, 100M).

The real failure is this (please ignore my earlier "WHAT FAILS" list):
- The PC's ARP request reaches ETH1 (ETH1 MMC broadcast counter increments, no CRC/alignment/length errors).
- The CPU sends the ARP reply (HAL status OK, 64 bytes + 2-byte management trailer "00 04").
- FES counts it: Port0 RX_UNICAST=1 / RX_GOOD_OCTETS=70, Port2 TX_UNICAST=1 / TX_OCTETS=68.
- BUT Wireshark on the PC shows only repeating ARP requests and never the reply.
- Port2 RX_UNICAST=0 is only a consequence: the PC sends no unicast until ARP resolves.

Already checked: VLAN 0/1/0xFFF members=0x7, VLAN0R=0x8FFF, no VLAN tag added.
ETH1 direct mode works with the same PHY and cable. Linux with the switch works at 100M and 1000M.
SYSCFG_ETH1CR reads 0x10 in Linux; I tested 0x10 and 0x12 in bare-metal.
[ADD AFTER WIRESHARK CHECK: A broadcast test frame sent by the CPU on the same path (Port2 TX_BROADCAST=1) is / is NOT visible on the PC.]

1000M / HW_MODE_GMII (correction): the counters do increment, but every frame is counted as bad.
Port2 RX_BAD_OCTETS=8000 with RX_64=125, RX_GOOD_OCTETS=0, and RX_ERR / RX_CRC_ERROR /
RX_UNDERSIZE / RX_FRAGMENTS all 0. The Dynamic MAC Table stays empty. Linux works at 1000M.

QUESTIONS
1. For frames sent by the CPU through Port0 (Management mode), is any EIA or FES setting needed for
   Port2 to actually transmit, besides FES_PORT_STATE, forwarding and the EIA link status?
   Is there any EIA status or counter that shows a frame was sent to the PHY?
2. In Linux, FES_FID_CFG0R of Port2 reads 0xAAAAAAAA (32-bit read of 0x4C220080), while Ports 0 and 1
   read 0. Bare-metal writes 0 on all ports. What does this register do? Is it needed for unicast forwarding?
3. At 1000M in HW_MODE_GMII, which conditions increase RX_BAD_OCTETS without increasing RX_ERR,
   RX_CRC_ERROR, RX_UNDERSIZE or RX_FRAGMENTS?
4. Which bits of a Dynamic MAC Table entry hold the port number and the FID?
5. Is the 16-bit management trailer the default after the INIT_REQ pulse? (GEN_CTRLR reads 0x0000 right
   after the pulse and 0x0004 after 300 us.) Must the other trailer bits (MAC sec, SMD, IPO) be zero
   for normal traffic?
6. Is there an ST bare-metal example or driver for ETHSW/EIA, or a documented init sequence for
   Port0 in Management mode with ETH1 at 100M?