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The official STM32U0 SVD version 1.0 files for STM32U031, STM32U073, andSTM32U083 specify:  <nvicPrioBits>4</nvicPrioBits>The manual (RM0503) documents four programmable interrupt priority levels implemented withtwo priority bits. ST's own current CMSIS device headers also specify thecorrect value:  stm32u031xx.h: #define __NVIC_PRIO_BITS 2  stm32u073xx.h: #define __NVIC_PRIO_BITS 2  stm32u083xx.h: #define __NVIC_PRIO_BITS 2The svd metadata files are used in the rust ecosystem as well as other third party tooling.SVD code generators exposing this value to software firmware.I’m using the rust RTIC framework along side stm32/stm32-rs crate which depend on the SVD for source oftruth configuring for various stm32 MCUs.The issue above manifests in the following bug in that framework:In stm32-rs/stm32-rs, svd2rust generated `NVIC_PRIO_BITS = 4` fromthe ST SVD. RTIC then converted logical priorities using four bits. Logicalpriorities 1, 2, 3, and 4 were written as 0xf0, 0xe0, 0xd0

Summary STM32CubeMX (STM32U5 targets; reproduced with 6.18.0-RC3 and 6.18.1-RC2) generates an incorrect clock-disable call in the LSE bring-up block of HAL_RTC_MspInit() in Core/Src/rtc.c. The restore path that is meant to switch the PWR peripheral clock back off passes an AHB3 peripheral mask to the APB1 disable function:/* Restore clock configuration if changed */if (pwrclkchanged == SET){LL_APB1_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PWR); /* generated — wrong bus group */}The matching enable earlier in the same function is generated correctly:if (LL_AHB3_GRP1_IsEnabledClock (LL_AHB3_GRP1_PERIPH_PWR) != 1U){/* Enables the PWR Clock and Enables access to the backup domain */LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);pwrclkchanged = SET;} DiagnosisOn the STM32U5, the PWR peripheral clock lives on AHB3, and the two enable registers happen to use the same bit position:Register Bit 2 Reference RCC_AHB3ENR PWREN — PWR clock enable RM0456 Rev 5, §11.8.32, p. 558 RCC_APB1ENR

Hi All,im currently trying to get an UL approval for one of our products which uses the VL53L5CX sensor. Now, they require a full CB Test Report (not only a CB certificate). My question is: can ST provide this test report for their costumers? Also, since i can’t be the first person trying to achieve a UL approval for a porduct using a ST ToF sensor, i would be interested in your experiences regarding this matter.   

Hi, I am currently working with the LPS25HB chip, which performs well overall. However, once integrated into my device, I observed a consistent offset in the pressure readings. To address this, I applied an offset correction, and the readings became accurate. During initial testing with 15 devices, each unit required an individual offset adjustment. After applying these corrections, all devices reported pressure values within a similar range.My device is enclosed in a circular case with a small opening positioned directly above the sensor. As I move toward mass production of over 1,000 boards, assigning offsets individually becomes a significant challenge. Based on my testing, it appears that offset calibration is mandatory. I would appreciate your guidance on how to streamline this process. Specifically:Recommended steps to assign offsets efficiently during mass productionAny soldering guidelines, such as temperature considerations, to minimize offset issuesSuggestions for alternative

Issue summary:Unable to establish a debug connection between the PLS UDE software and the board's onboard JTAG debugger. Every connection attempt fails with the same error:"FtdiCommDev: Failed to open FTDI device driver"Troubleshooting completed:- Tested on 2 different physical SPC56B-Discovery boards — identical failure on both, ruling out a defective board- Tested 2 different UDE software versions (5.2.04 and 2021.05) — identical failure on both- Fully uninstalled and reinstalled the USB/JTAG driver multiple times, including a full PC restart in between- Confirmed the driver installs correctly and shows in Windows Device Manager with no errors- Ran UDE with Administrator privileges- Tested multiple USB ports- On a separate occasion, Windows itself reported a hardware-level fault (Device Manager Code 43: "device descriptor failed") for the same connectionConclusion:Since the software, drivers, and board all check out, but the actual USB communication still fails, this points to a comp

LSM6DSV80X: Measured Accelerometer 3 dB Bandwidth Lower Than ODR/2 — LPF1 Only EnabledHello ST Community,In our new application, we are using the LSM6DSV80X IMU, which has independent low-g (XL) and high-g (HG) accelerometer channels.Our configurationAccelerometer ODR: 960 Hz for both XL and HG. Accelerometer operating mode: High-performance]. Accelerometer filtering: LPF1 enabled, LPF2 disabled. HP_SLOPE_XL_EN = 0 and LPF2_XL_EN = 0 for the XL low-pass path. Frequency-response measurement performed using a controlled vibration input.Observed frequency responseWe measured the following approximate −3 dB bandwidths: Accelerometer channel Datasheet expected BW Measured −3 dB BW High-g (HG) ODR/2 = 480 Hz Around 400 Hz Low-g (XL) ODR/2 = 480 Hz Around 350 Hz The measured frequency response was obtained by comparing the peak-to-peak acceleration output at different input frequencies against the low-frequency reference.Ques

I've come across an issue where the generated cmake/flags.cmake contains an error causing the build to fail for .cpp files.The same file is generated when creating a new empty project with clang toolchain. STM32CubeIDE for Visual Studio Code: 3.10.0Toolchain:                           ST Arm Clang 21.1.1MCU:                                 STM32H723ZGT6 Generated in cmake/flags.cmake:$<$<COMPILE_LANGUAGE:CXX>:    ...    -std=gnu11> Result:[build] error: invalid argument '-std=gnu11' not allowed with 'C++' Removing -std=gnu11 from the CXX section of flags.cmake fixes the build. 

Kindly suggest the root cause 

Hello everyone,I am working with an STM32H743 running at its maximum frequency of 480 MHz. I am trying to implement VBlank synchronization using the LTDC Line Interrupt and CMSIS-RTOS v1 (FreeRTOS). My goal is to unblock a display/rendering task at every frame interval.According to my hardware configuration, the frame time should be 16.6ms (60Hz refresh rate). The mathematical formula confirms this:Total Width = 920, Total Height = 542, Pixel Clock = 30 MHz. (920 * 542) / 30,000,000 Hz = 0.01662s -> 16.62ms.My FreeRTOS configuration is strictly set to configTICK_RATE_HZ = 1000 (1 tick = 1ms).The Problem & Debugging History:Initially, I placed three hardware breakpoints in my code to track execution flow:(1) Right at osSemaphoreWait in the task loop. (2) Inside the HAL_LTDC_LineEventCallback after re-programming the line. (3) Right at the gm_sprintf line where time delta is formatted.If the synchronization loop worked correctly, the debugger should have hit these breakpoints sequ

Hello ST Community,I am working on an STM32N6 project where I need to implement a USB composite device containing three distinct classes: CDC ACM Instance 1 CDC ACM Instance 2 UVC (USB Video Class) Current Status & Setup:The dual CDC ACM implementation is fully stable and working properly. I generated the basic framework using STM32CubeMX (.ioc), which handles the initial USBX configuration, the first CDC instance, and sets up the composite device configuration. Following that, I manually added the second CDC ACM instance code to the project.On top of this working multi-CDC setup, I now want to integrate the Video Class layer. I have enabled the core video class inside the .ioc file and regenerated the code to expand the descriptor framework.The Challenge:To support high-bandwidth Isochronous (ISO) streaming for the Video class component, I integrated the uvcl (USB Video Class Library) middleware extracted from the ST Edge AI Getting Started exampleThe issue started exactly upo

Hello, We are using Keil MDK with version 5.27 for our firmware developement. We want to start using STM32C5 series and I wanted to use software packs for STM32C5 series by using pack installer in Keil. But it is not possible to download this pack with Keil and also imprting this pack to Keil is not supported. What could be solution for this when we want to retain our IDE as Keil. Our license for Keil supports only for this v5.27. 

Product https://www.st.com/en/mems-and-sensors/lsm6dsox.htmlAbout the below datasheet description, I want to confirm exact I2C Fast mode Plus timing. Should this SETDASA/ENTDAA follow all timing parameters as I2C Fm+? For NXP I3C, it’s not hard to set a suitable baud rate for this, but it’s impossible to meet all timing for a ENTDAA operation. Can ST I3C IP run ENTDAA with I2C timing to meet your sensor product?  

I would like to ask for the clangd bundle shipped with the STM32Cube clangdextension to be rebuilt against a newer LLVM, so that it picks up theclang-format changes released in LLVM 23.Environment-----------VS Code extension : STM32Cube clangd 1.0.6clangd bundles    : st-arm-clangd 19.1.2+st.3 and 21.1.0+st.2                    (%LOCALAPPDATA%\stm32cube\bundles\st-arm-clangd)Host              : Windows 11What is missing---------------clang-format 23 accepts a path in `BasedOnStyle`, for example:BasedOnStyle: InheritParentConfig=some/directoryThis tells clang-format to read the .clang-format of that directory andapply the current file on top of it. It was requested inhttps://github.com/llvm/llvm-project/issues/107808 and is present inclang-format 23.1.0. Both ST bundles still carry the older syntax only:the string "InheritParentConfig" is in the binaries, but the "=<path>"form is not.The request-----------1. A clangd bundle built from LLVM 23 or later, so that the formatter   unde

  Hi,       Summary. The ONNX importer in ST Edge AI Core 2.2.0 (X-CUBE-AI 10.2.1) ignores the  dilations attribute of Conv. It applies the padding but convolves as if dilation = 1,  so the output length is L + 2*pad - (k-1) instead of L. The TFLite importer handles  the same operator correctly.  Minimal reproducer (attached, 51 KB): a single Conv1d(64->64, kernel 3, dilation 4,  padding 4), input 1x64x80. The ONNX node is Conv {pads:[4,4], strides:[1], dilations:[4]}.  Per the ONNX spec the output is (80 + 4 + 4 - ((3-1)*4 + 1)) / 1 + 1 = 80.  PyTorch and onnxruntime both produce 1x64x80.      stedgeai analyze --model dil_f32.onnx --target stm32u5  | model handed to stedgeai                      | reported output     | expected |  |------------------------------------------------------|-------------------------|--------------|  | ONNX float32                                          | f32(1x64x86)       | 1x64x80  |  | ONNX int8 QDQ (per-channel)               | int8(1x64x86)     

Hi,I am trying to use NanoEdge AI to develop an N-class fault classification model for helical gearboxes that will eventually run on an STM32 MCU.The challenge is that I have many different helical gearboxes, and their physical parameters vary significantly, including:Input RPM and output RPM Gear ratios Number of teeth Bearing types and sizes Gearbox dimensions and load capacitiesI currently have around 20 fault classes that I would like the model to detect.Has anyone successfully created a generalized model that can classify gearbox faults across multiple gearbox variants rather than training a separate model for each gearbox?What would be the recommended approach in NanoEdge AI for handling such variability while still achieving good fault classification accuracy on embedded hardware? Any guidance, examples, or best practices would be greatly appreciated.Thanks!

Hi all,I’m trying to follow this guide here but when I try to run the model on target I always got an error failed to erase memory.Here is the log. I’ve also set external loader from cubeprogrammer to MX66, and if I try to erase memory from cube programmer I also have an error, loose comunication with the boardSaving workspace.[36m[01m -------------------------------------------------------------------[39;49m[0m[36m[01m STM32CubeProgrammer v2.23.0 [39;49m[0m[36m[01m -------------------------------------------------------------------[39;49m[0m[39;49m[0m[90mST-LINK SN : 004700233234510E37333934[39;49m[0m[90mST-LINK FW : V3J17M11[39;49m[0m[90mBoard : STM32N6570-DK[39;49m[0m[90mVoltage : 2.75V[39;49m[0m[90mSWD freq : 8000 KHz[39;49m[0m[90mConnect mode: Under Reset[39;49m[0m[90mReset mode : Hardware reset[39;49m[0m[90mDevice ID : 0x486[39;49m[0m[39;49m[0m[39;49m[0m[39;49m[0m[90mRevision ID : Rev B[39;49m[0m[39;49m[0m[39;49m

i recently install STM32cube IDE2.2.0 in my laptop and i m not able to generate .ioc file not pin configuration please give some solution.

Greetings.I'm a Linux user, I use Windows on a smaller notebook for tools like TouchGFX, but this is quite inconvenient.Is there any plan to release a Linux version of TouchGFX Designer?I saw in the documentation that there's a simulator and that it can even be used with Wine; I'll test it today, but it would be really good to have a native version.Link where I saw information about the simulator: https://support.touchgfx.com/docs/introduction/prerequisitesthanks

Hello,I am using an STM32L4R9ZIT6 in a new project. After replacing the MCU with a new one, the LSE oscillator stopped working. And the MCu doesn’t start until one activates the LSI.To troubleshoot the issue, we have:Replaced the crystal Tried different capacitor values Verified that the crystal works normally in another setupSince the only change was the MCU replacement, we are wondering what could be causing this problem. Do you have any suggestions on possible causes or additional checks we should perform?Thank you in advance for your help.Best regards,Roland

The new tooling is nice and the UI is much cleaner to navigate with.Positive Feedback ​@MorkBeck:We love the VS Code direction YES, it would be helpful to get H5 on here as well as it would keep our code bases aligned. AI? No thank you, “focus to stay on reliability, documentation quality, and API maturity”. As anyone savvy knows, AI scrapes those docs anyways. Good docs and samples help a lot.A few of issues we’re running into that are major speed bumps. I don’t know where your bug list is at to report or to see if it’s tracked:Code Generation overwrites our `main.c` EVERY TIME. Yes it’s documented above, yet this is painful. The `*.c.base@x.y.z” files are just absolute clutter!  “YAGNI” - You Ain’t Gonna Need It And i can’t disable it either, that option is always grayed out. Upgrading from CubeMX2 v1.01 to 1.1.1 Broke the EXTI configuration screen, and the page NEVER renders. Causes other lack of functionality issues Feel free to reach out to me. Inability to pull Packs dynamica

Using a new ST-LINK/V2，it always Error: Problem occured  while trying to connectI use the wire I bought before to connect it, it will be OKI want to know why this is 

Dear ST Community Team,I am working on an STM32H747 project with a custom bootloader and OTA update mechanism. The OTA download completes successfully, metadata is written, and CRC verification passes. However, after the OTA apply step, the device does not reboot into the new firmware. The system continues running the old application, and I never see the expected reboot message from the bootloader.Details: Device: STM32H7 series Bootloader checks metadata at 0x081E0000 Staging slot at 0x08100000, App slot at 0x08020000 OTA side writes metadata fields (magic, version, staging base, app base, slot size, image size, CRC) Logs show: "Download OK" and "Applying..." but no reboot occurs

Hello ST team,I noticed what appears to be a documentation typo in the STM32MPU Wiki page “How to configure TSN switch”, section 3.1 – Run the PTP stack.The documentation states:“dePTP stack is started by default. To start it using via systemctl:”but the command shown immediately after that sentence is:systemctl stop deptpI believe the intended command is:systemctl start deptpThis is also consistent with the later “How to trace the PTP stack” section of the same page, where the documentation correctly uses:systemctl stop deptpto stop the service, and:systemctl start deptpto start it again.The Qbv section also states that gPTP synchronization should be started beforehand and thatdeptpis started by default.Could you please confirm and correct the command in section 3.1 if this is indeed a documentation typo?Thank you.

Hello,Is it possible to pull Vref- lower then Vss? For reverse voltage protrection I use a diode and a resistor to create GND1. GND1 is then connected to VSS of the µC.Scematic. All caps omittedCan I connect Vref- to GND? See Image.Datasheet stm32c542ccThe datasheet does not specify.If I connect Vref- to GND1 all values i measure with the ADC must be against GND1 otherwise the result is off by the offset of GND1 to GND.

Hello, I’m having some issues connecting my sensor tile box pro to my pc via a USB cable and with an ST-Link V2. I’ve followed the documentation regarding DFU mode, and the board doesn’t respond to it in STM32 Programmer ( I’ve double checked  if its a data cable, and this was confirmed). With the ST-Link, my Device Manager recognizes the debugger, but it has issues communicating/connecting with the board. However, I am able to flash it via Bluetooth. Is there some initialization I missed?