[STM32F7] BKPSRAM lost after hard reset

[SGheo.1]

Hello,

 

I’m working of a TM32F769 board the content of the 4 KB backup SRAM (BKPSRAM,
0x40024000) is lost after a hard power cycle (VDD removed and re-applied),
although:

  - VBAT is supplied by a 3 V lithium coin cell (Renata, CR1225-type),
  - the backup regulator is enabled (PWR_CSR1.BRE = 1) and ready
    (PWR_CSR1.BRR = 1) before power-off, and BRE is still set at the next
    cold boot,
  - the rest of the backup domain is retained: RCC_BDCR keeps its value
    (LSE on/ready, RTCSEL = LSE, RTCEN = 1) and the RTC keeps running,
  - HAL_PWREx_EnableBkUpReg() returns HAL_OK,
  - BKPSRAM content IS retained across system resets (NRST / IWDG) while
    VDD stays present.

 

The test I have performed:

 1. Flash and run the firmware once (writes 0xDEADBEEF to BKPSRAM word 0).
 2. Disconnect the ST-LINK cable from the board (to avoid back-powering
    through SWD pins).
 3. Remove all board power (VDD). The coin cell stays connected to VBAT.
 4. Wait for 5 min.
 5. Power the board up without the debugger and let it boot.
 6. Connect the ST-LINK and attach without reset (Reset behaviour = None,
    no download, core resumed) and read the globals via Live Expressions
    without halting the core.
 

Result: BKPSRAM has garbage value.

Could you please provide any hints on what might be the issue?

 

[waclawek.jan]

I don’t know the reason for failure, but how is VDDA connected?

JW

[KDJEM.1]

Hello ​@SGheo.1 ;

 

First of all I recommend you to check the configuration mentioned in RM0410 Rev 5 to retain backup SRAM.

To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source.

To allow the RTC to operate even when the main digital supply (VDD) is turned off, the VBAT pin powers the following blocks:

• The RTC

• The LSE oscillator

• The backup SRAM when the low-power backup regulator is enabled

• PC13 to PC15 I/Os, plus PI8 I/O (when available)

The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset block

 

Thank you.

Kaouthar

[MM..1]

Live expression is buggy sometimes, stop code and read memory in expression or memory window

[Pavel A.]

Are any tamper pins enabled? Glitch on a tamper pin can trigger erase of backup RAM.