IIS3DWB10IS: registers 0x01–0x12 go to 0x00 mid FIFO burst read (SPI mode 3), even with DBG1 tied to GND
Hi all. We're streaming the IIS3DWB10IS FIFO over 4-wire SPI, mode 3, at 8–10 MHz (on a STEVAL-MKI253KA with a ~15 cm cable). Now and then the part loses its configuration. Registers 0x01–0x12 all read 0x00, while 0x13 and above keep their values and WHO_AM_I still reads 0x50. The zeroed registers include PLL_CTRL_2, which we never write, and PIN_CTRL, IF_CFG and CTRL3, which have non-zero POR values. So it isn't a reset.
On the logic analyser (500 MS/s), CS stays low for the whole burst, SCK has exactly the right number of clocks, and SDI is 0x00. Then, 50–80 bytes into the FIFO burst, the sensor stops driving SDO at a byte boundary. INT1 rises within ~100 ns of that moment and falls again 9 bytes later. That is exactly when a "write from 0x00" re-framed at that byte would reach FIFO_CTRL3. It looks as if the SPI frame restarts internally and our 0x00 dummy bytes are taken as a write.
The eval board ties DBG1 to GND only through 1 MΩ, where the datasheet says it must be tied to GND. Bridging that resistor took a stress test from 4 failures in 4 runs to 0 in 3, but we've just seen it again after 5.7 h of normal streaming.
Has anyone seen this on the IIS3DWB or IIS3DWB10IS? Does the AN5444 mode-3 note (CS low with SCK high for 25 µs or less; mode 0 recommended for FIFO reads) apply to the 10IS? Is there a recommended FIFO burst length or dummy byte value? We've also opened an ST support ticket (number to follow). The register dumps are attached.
