About DreamOnDirac

DreamOnDirac · 2023-09-18

HiEarlier today I was demonstrating a IAP functionallity with dualbanking on a stm32G474RET. I was saying that it cannot fail as I check the written image with a CRC after it has been written to the new bank.As I power of the system mid transfer and ...

DreamOnDirac · 2023-09-15

HiAssume that i set up an H-bridge and and control it via the HRTIM block and use the build in deadtime features. I then also enable a couple of faults. The bridges safe state will be to set both lower transistors to be OFF and the two upper once to ...

DreamOnDirac · 2023-10-06

HiIf anyone else finds this thread.I did not succeed in using hardware to fix this. Instead i made sure that any faults made sure that the entire H-bridge was drawn low and I then set the HRTIM FLT interrupt to be the highest priority in the system:I...

DreamOnDirac · 2023-10-02

(Deleted by author)

DreamOnDirac · 2023-10-01

Hi @Pierre_P How sure are you on this? I discovered this presentation:https://www.st.com/content/ccc/resource/training/technical/product_training/group0/58/ad/f9/d5/64/2b/49/05/STM32G4-WDG_TIMERS-High_Resolution_Timer_HRTIM/files/STM32G4-WDG_TIMERS-H...

DreamOnDirac · 2023-09-26

Hi TDK and thanks for the suggestion.I ended up doing the same thing as that thread suggested. After around 60 attempts cut power while programming the flash, the error triggered.I got "lucky" after that and the next time i needed to trigger it it to...

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