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STM32H5 FLASH_ECCDETR address decoding

Associate III

In the FLASH_ECCDETR register, the ADDR_ECC field description contains:

"The address in ADDR_ECC is relative to the flash memory area where the error occurred
(user flash memory, system flash memory, data area, read-only/OTP area)."

But I'm having trouble decoding the actual address where the double ECC bit error occurred.


For instance, I have configured EDATA areas of 8 sectors in both banks.

Reading from an uninitialized EDATA sector at address 0x09006000 (which is the 5th EDATA sector in BANK1) results in an ECCD NMI, with FLASH_ECCDETR value 0x8020F800

So ECCD and  EDATA_ECC bits are set, as expected, but the ADDR_ECC equals 0xF800.

How do I convert that to 0x09006000, or to 0x6000, given that the address is supposed to be relative to the flash memory area where the error occurred?


And similar for OTP, if I read from (uninitialized) OTP address 0x08FFF000 (which is FLASH_OTP_BASE), FLASH_ECCDETR value is 0x81000600.

How do I convert that 0x600 to 0x0?

In fact, I read a 32bit word, and I get two NMI's with 0x81000600 and 0x81000601.

So for OTP the ADDR_ECC seems to count in halfwords.
But converted to byte addressing that would result in 0xC00 and 0xC02, I'm wondering where does this 0xC00 offset come from?


For EDATA, I only get a single NMI for a 32bit read by the way.

Reading 0x09006000 results in ADDR_ECC 0xF800

Reading 0x09006004 results in ADDR_ECC 0xF801

So for EDATA the ADD_ECC seems to be counting 32bit words instead of halfwords.

Converted to byte addressing that would result in 0x3E000 and 0x0x3E004, where 0x6000 and 0x6004 would be expected, a difference of 0x38000. Where does this 0x38000 offset come from?

And even more confusing, the next EDATA sector:

Reading 0x09007800 results in ADDR_ECC 0xFA00

Reading 0x09007804 results in ADDR_ECC 0xFA01

Converted to byte addressing that would result in 0x3E800 and 0x3E804, an offset of 0x37000 instead of the 0x38000 which we found for the previous EDATA sector.


And finally, as it seems that for EDATA ADDR_ECC counts in 32bit words, and we get only one NMI per 32bit word read, why is the FLASH_ECCDR DATA_ECC field only 16 bits wide?

In order to retrieve the error data, I would either expect 32bit DATA_ECC, or expect two ECCD NMI's for a 32bit read, with two 16bit DATA_ECC values for the two halfwords.

Associate III

Am I the only one struggling with this?

Or is everyone just ignoring ECC error NMI's?