About DAlbe.3

DAlbe.3 · 2024-05-30

Erratum 2.2.1 (Unstable LSI when it clocks RTC or CSS on LSE) indicates the following workaround:If LSI clocks the RTC or when the LSECSSON bit is set, reset the backup domain upon each VDD power up(when the BORRSTF flag is set). If VBAT is separate ...

DAlbe.3 · 2024-05-27

I would like to increase the code readout protection level from 0 to 1 programmatically in an STM32G030. I must be doing something silly and if anyone sees it, I'd be grateful. I've stepped through it with the debugger and the flash and option byte...

DAlbe.3 · 2024-05-23

EDITED:Resolved, but leaving here for the next person who stumbles into this issue.I'm using the STM32G030K6 and encountered two issues:Errata 2.2.3 - which correctly describes a serious issue when using readout protection level 1: if nBOOT_SEL is no...

DAlbe.3 · 2024-01-26

I have a small amount of per-device data (e.g. hardware revision, serial number, manufacture date) that I would like to store persistently in an STM32G030 without consuming a 2K flash sector. Obviously one option is OTP, but I'm curious about the Fl...

DAlbe.3 · 2023-08-18

When used on STM32L4xx platforms (and possibly others), with flash configured for single-bank mode, the EEPROM emulation library (https://www.st.com/en/embedded-software/x-cube-eeprom.html) miscalculates flash sectors which causes silent erase failur...

DAlbe.3 · 2024-06-06

Hi @Uwe Bonnes, nRST option bits are not touched (they stay at the factory default; I can check what that is if you want, but external reset is functional). nRST has a 100nF to ground but no pull-up; if a pull-up is recommended, then that may be an...

DAlbe.3 · 2024-06-06

Hi @Bubbles,Thank you again; I understand the skepticism and am happy to share whatever details I can. The component is the STM32G030K6T6 (LQFP32); it does not have separate VDD and VBAT pins. Power is 3v3 via an XC6216D332PR LDO with 1uF on the in...

DAlbe.3 · 2024-06-06

Thanks @Attila_Horvath, in my case, I start the IWDG in software after the workaround (reset the backup power domain and start LSI. The first code that runs in main() is: // For development firmware (odd version #), disable IWDG when core stopped...

DAlbe.3 · 2024-06-06

Testing was done at room temperature and the uC Vdd rail is supplied by a 3v3 LDO.

DAlbe.3 · 2024-06-06

I start the IWDG in software

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User Activity

STM32G030 erratum 2.2.1 workaround is not reliable

How to set RDP level 1 via software on STM32G030

STM32G030 readout protection level 1 (errata 2.2.3) POR lockup if boot select via BOOT0 pin enabled

STM32G030 spare option bytes

STM32L4xx (and maybe others) EEPROM emulation library bug with single-bank flash mode

Re: STM32G030 erratum 2.2.1 workaround is not reliable

Re: STM32G030 erratum 2.2.1 workaround is not reliable

Re: STM32G0 Unstable LSI frequency

Re: STM32G0 Unstable LSI frequency

Re: STM32G0 Unstable LSI frequency