STM32G0 Unstable LSI frequency

[Attila_Horvath]

Dear Everyone,

We use STM32G0B0 MCU and in errata there's a section from the unstable LSI frequency. In some case the LSI frequency about 48 kHz. The workaround not work, after backup domain reset, the LSI frequency still about 48 kHz.

My theory is that, the IWDG is running, so the backup domain reset cannot turn off LSI. Someone has a valid workaround or some ideas how I can force the backup domain reset if the IWDG running? Unfortunately POR not an option...

Br,

Attila

[DAlbe.3]

Testing was done at room temperature and the uC Vdd rail is supplied by a 3v3 LDO.

[DAlbe.3]

Thanks @Attila_Horvath, in my case, I start the IWDG in software after the workaround (reset the backup power domain and start LSI.  The first code that runs in main() is:

    // For development firmware (odd version #), disable IWDG when core stopped in debugger
    if (fw_version & 0x0001) { // development version
        SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN);
        SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP);
    }

    // Enable PWR control, SysCfg subsystems, GPIO Ports A, B, C
    SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); // enable clock to pwr control subsystem
    SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN);
    SET_BIT(RCC->IOPENR,  RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN);

    // Start LSI oscillator used by RTC and IWDG
    SET_BIT(PWR->CR1, PWR_CR1_DBP);           // enable access to backup power domain
    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET);
    // See Errata 2.2.1: Unstable LSI after main power domain reset
    // if reset was due to POR or BOR, reset the backup power domain
    if (RCC->CSR & RCC_CSR_PWRRSTF) {
        SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);       // reset backup power domain
        while(READ_BIT(RCC->BDCR, RCC_BDCR_BDRST) == RESET);
        CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
    }
    // Start LSI and wait until ready
    SET_BIT(RCC->CSR, RCC_CSR_LSION);         // turn on LSI oscillator
    while (!(RCC->CSR & RCC_CSR_LSIRDY));     // wait for LSI ready
    CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);

    // Initialize hardware watchdog (depends on LSI)
    watchdog_init(2000); // 2s timeout