About Christophe VRIGNAUD

Christophe VRIGNAUD · 2024-12-19

Introduction RCC clocks can be internally connected to timers. The points addressed here are the following: Finding which clock is connected to which timer.Finding how the clock is connected to a timer.Implementing this connection in STM32CubeMX. Thi...

Christophe VRIGNAUD · 2024-10-22

STM32 FDCAN - How to avoid some communication disruption by choosing appropriate clock values compared to the desired time quantum.

Christophe VRIGNAUD · 2023-09-14

How to find the RAM ECC failing address? How to access to the right RAMECC monitor to get the RAM failing address when an ECC error occurs?How to translate the content of the failing address register to the actual RAM address (e.g. FADD= 0x2004)? No...

Christophe VRIGNAUD · 2022-06-02

How to find the RAM ECC failing address? How to access to the right RAMECC monitor to get the RAM failing address when an ECC error occurs?How to translate the content of the failing address register to the actual RAM address (e.g. FADD= 0x2004)?Not...

Christophe VRIGNAUD · 2021-07-22

How to use STM32 HAL UART driver API and Callbacks?What are the callbacks involved in UART TX / RX?How are these callbacks called?Why is the callback not called? 1. STM32 HAL UART supports 3 modes for transmitter (TX) / receiver (RX) Polling mode (no...

Christophe VRIGNAUD · 2024-10-18

Hello @bipin_g, You should give at least your IRQ handler code if you want to get some answer. As far, you can search for "irq handler gets called continuously" in your browser. I've found the following links which could perhaps help. c - USART1_IRQH...

Christophe VRIGNAUD · 2024-09-26

Hello, First of all, on the STM32H753xI, the RAM ECC can't be turned off. It can't be enabled/disabled like on the STM32H5 or STM32U5. You can refer to Guide: Injecting and Handling ECC Errors in RAM and Flash on STM32H7 - STMicroelectronics Communit...

Christophe VRIGNAUD · 2024-07-12

Hi @theHolgi From which IDE does this screenshot come from? And which version of the tool? On which OS?Which debugger do you use? (I've found a picture of STM32CubeIDE on MacOS with JLink displaying the SFRs in the memory view: from this I would gue...

Christophe VRIGNAUD · 2024-07-03

Hi @theHolgi RAMECC1_M1SR is the status register of RAMECC1 monitor 1 = 0x52009024. This is the AXI SRAM monitor. As RAMECC1_M1FAR (0x52009028) = 0x3ffd, the ECC failure is in AXI SRAM at address: RAM failure address = 0x2400 0000 + 0x3ffd * 8 = 0...

Christophe VRIGNAUD · 2024-07-01

Hi @KORourke In STM32H743 or other STM32H7 series, only DTCM has this interleave specificity.The AN5342 has a special focus on the STM32H5 and STM32H7 series microcontrollers but doesn't concern only these microcontrollers. It is also dealing with f...

User statistics

User Activity

STM32H5: How to interconnect RCC clocks to timers

FAQ: Fixing STM32 FDCAN communication disruptions - APB bus, kernel, and time quanta clocks

FAQ: STM32H7 - How to read RAMECC_MxFAR failing address

FAQ: STM32H7 - How to read RAMECC_MxFAR failing address

FAQ: STM32 HAL UART driver - API and Callbacks

Re: Getting continuous interrupts on USART

Re: How to inject ECC Error into RAM on the STM32H75

Re: FAQ: STM32H7 - How to read RAMECC_MxFAR failing address

Re: FAQ: STM32H7 - How to read RAMECC_MxFAR failing address

Re: FAQ: STM32H7 - How to read RAMECC_MxFAR failing address