Posted on May 17, 2011 at 12:56My point is, that - from the ref manual - it is not possible to use the multiplexed timing in conjunction with 8-bit access. Perhaps ST can clarify this point.
Posted on May 17, 2011 at 12:56I am not sure, but I think multiplex access is only valid with NOR-Flash timing and with NOR-Flash timing it is not possible to set the data-bus to 8 Bit. See table 74, page 373 in RM0008 and the hint on page 394 (MUXE...
Posted on May 17, 2011 at 12:54one solution is to set the pending bit of the irq at the end of the isr: irq_pending_bit = ! irq_level It is only one instruction and everything should work.
Posted on May 17, 2011 at 12:52LDR is a pseudo instruction. If you load a program address, it switches the LSB to 1 to indicate the Thumb-State of the processor. If you load a data address the LSB is not changed. A second way is to use ADR, then the...
Posted on May 17, 2011 at 12:51there is one register set for each memory device, so you have to program the FSMC controller only once. The mapping: memory address -> chip select -> address of register set is hard-wired (see RM0008 page 368 (table 66...
