SRAM multiplexed on FSMC

denkov · ‎2008-12-20

Posted on December 20, 2008 at 18:29

denkov · ‎2011-05-17

Posted on May 17, 2011 at 12:56

Hi all. I'm trying to drive ext. SRAM(55ns) muxed on FSMC port (MCU: ...103vc-100 pin).

The control signals is look good on my SCOPE.

When I'm write some array data in the ExRam segment the

results is writing address indexes (0,1,2,3.....)

I'm using this setings..

FSMC_AccessMode_D;

FSMC_Bank1_NORSRAM1;

FSMC_DataAddressMux_Enable;

FSMC_MemoryType_SRAM;

FSMC_MemoryDataWidth_8b;

FSMC_BurstAccessMode_Disable;

FSMC_WaitSignalPolarity_Low;

FSMC_WrapMode_Disable;

FSMC_WaitSignalActive_BeforeWaitState;

FSMC_WriteOperation_Enable;

FSMC_WaitSignal_Disable;

FSMC_ExtendedMode_Enabled;

FSMC_WriteBurst_Disable;

10X

tibo · ‎2011-05-17

Posted on May 17, 2011 at 12:56

I am not sure, but I think multiplex access is only valid with NOR-Flash timing and with

NOR-Flash timing it is not possible to set the data-bus to 8 Bit. See table 74, page 373

in RM0008 and the hint on page 394 (MUXEN).

See also:

denkov · ‎2011-05-17

Posted on May 17, 2011 at 12:56

I can't see any difference in SRAM and NOR timing diagrame.

Did anybody succeed multiplexing NOR or SRAM ?

sjo · ‎2011-05-17

Posted on May 17, 2011 at 12:56

I have been helping a customer out who had designed their hardware for multiplexed sram - their old design was doing the same thing with a str9.

They missed the info in the ref manual and presumed it would work.

ST told us it could not be done but we tried anyway - so far it seems to be working ok for 8/16/32bit accesses.

In the end we chose CRAM (PSRAM) mode with burst and wait disabled.

Use this info at your own risk!!

Cheers

sjo

tibo · ‎2011-05-17

Posted on May 17, 2011 at 12:56

My point is, that - from the ref manual - it is not possible to use

the multiplexed timing in conjunction with 8-bit access. Perhaps ST

can clarify this point.

denkov · ‎2011-05-17

Posted on May 17, 2011 at 12:56

We Have a solution...

Using 74HC573 and latching addresses on NADV LOW

(make a latch transparent )