FSMC interface

[tibo]

Posted on September 12, 2008 at 14:57

FSMC interface

[tibo]

Posted on May 17, 2011 at 12:43

hi all,

we want to use the FSMC interface of the 100 pin STM to communicate with a FPGA device with embedded RAM. The advantage is that it is possible to access the FPGA device direct with read/write instructions or with the DMA controller. To minimize the used IO's we want to use the following: - 8 bit bus with multiplexed address and data - only asynchronous transfers So, we are thinking to use the multiplexed NOR-Flash-Timing, which uses the following signals: - D0-D15 - A16-A25 - NE1, NADV, NOE, NWE - CLK, NWAIT For our interface we need only the following signals: - D0-D7 - NE1, NADV, NOE, NWE My questions: 1. Can we use the signals CLK, NWAIT (normally used for the synchronous mode) as normal GPIO's, because we are not using the synchronous mode or are the signals in use? 2. The device will have only a few bytes of embedded RAM (< 256), so the 8-bit address on the 8-bit multiplexed address/data bus is sufficient for our application. - Is it possible to program the NOR-Flash Timing with multiplexed and 8-bit access? - Can we use the signals D8-D15 as normal GPIO's? - Is it possible to use the signals A16-A25 as normal GPIO's? 3. The FSMC interface has a 16 * 32 bit write buffer. How can this buffer flushed by / sync with the program (by DMB/DSB??)? Or is it possible to disable the buffer?

[mark4]

Posted on May 17, 2011 at 12:43

I only see the FSMC on the 144-pin packages.

[lanchon]

Posted on May 17, 2011 at 12:43

> Can we use the signals D8-D15 as normal GPIO's?

> Is it possible to use the signals A16-A25 as normal GPIO's? I'm not familiar with the high density devices, but these points hold true in general on the STM32: -any pin can be set to GPIO regardless of peripherals behind it; the GPIO configuration is closer to the pin and takes precedence. (exception: some very weird pins such as oscillator pins.) -except if the pin is in analog mode, the peripheral(s) behind a pin that use it as an input will see the value even if if the pin is in GPIO input or output mode (see the GPIO pin schematic for the exact value when in output mode). [this means that you can resolve inter-peripheral conflicts in favor of the peripheral(s) using the pin as input simply by selecting one of the GPIO input modes for the pin.] -in analog mode, a constant low value will be seen by the peripheral(s). -in alt-function mode, in case of an inter-peripheral conflict of output values, you'll see the ORed value of all peripheral outputs. -in alt-function mode, in case of an inter-peripheral conflict of output-enable signals, the conflict will resolve in favor of actively driving the pin. (I think this last point is true, but it might not be.)

[tibo]

Posted on May 17, 2011 at 12:43

yes, you are right. Thank you, so question 1, 2b, 2c

are all answered. Question 2a and especially 3 are still open: Is it possible to program the NOR-Flash Timing with multiplexed and 8-bit access? The FSMC interface has a 16 * 32 bit write buffer. How can this buffer flushed by / sync with the program (by DMB/DSB??)? Or is it possible to disable the buffer? Has someone an idea/answer?

[jj]

Posted on May 17, 2011 at 12:43

My firm had a similar idea - using the smaller, less costly 100 pin FSMC device as a display controller. I advise some caution.

Now I acknowledge the expertise & dedication of lanchon - however I believe that several of your desired signals - especially CLK - may qualify as ''weird.'' I believe there is risk if you try to ''liberate'' this pin - can you be absolutely certain that the chip will behave during all modes/events? We have the 100 pin FSMC device on order - if you are ahead of us with hardware it may prove valuable for you to perform some experiments. Try NOT to confirm your hopes/desires - your signal only has to misbehave sporadically for your design to be unstable...

[tibo]

Posted on May 17, 2011 at 12:43

Our first board is a prototype board. On this board we will leave all unused FSMC

signals open or connect them to the FPGA, so we can test the behaviour and have the option to change thinks. Thanks.

[jj]

Posted on May 17, 2011 at 12:43

Very much like the flexibility and safety of your design. Suspect that you have free/excess pins on your fpga - enabling you to tie critical fsmc signals to both the fpga and an I/O tie-point. As you gain operating experience you may choose to ''kill'' the connection to the fpga -as you positively learn that signal is not needed.

I will post here as our 100 pin fsmc & boards arrive - appreciate learning how your investigation turns out too...