STM32G473 ADC - can't select asynchronous clock divider 1 or 2, even with low clock frequency

[tinkerer42]

Hi,

I'm using STM32G473 ADC and trying to feed its clock from the PLL P clock. I am not able to select a clock divider of 1 or 2 even when the PLL P clock is set rather low (11.2 Mhz). This is my clock configuration:

This shows CubeMx not allowing an async clock with divider of 1 or 2, only 4 and higher:

For reference, these are the frequency limits of the ADC from the datasheet:

Specifically, I'm at the 52 MHz max spec (single ended, multiple ADC's) but whatever CubeMX thinks my limit is, I'm not sure why I can't divide-by-1 a 11.2MHz clock!

Is this a bug and I should use manual lines of code overriding what CubeMX does? or am I missing something in my understanding of the ADC clock?

p.s. my goal is to get as close to my limit of 52 MHz as possible. The 11.2 MHz setting shown above was just to debug CubeMX's weird behavior.

Thanks!

[tinkerer42]

OK, I fiddled with the settings some more and discovered another thing: If I enable only ADC1 and ADC2 (or just ADC1) then I can select my prescaler as expected. However, if I enable ADC3 as well, then I can't select /1 or /2, only /4 or higher, as noted in my original post.

I can't find a reference to this limit in the datasheet. Why is that?