1) When changing HPRE prescaler only CubeMX unexpectedly changes timer clock limits.
I think those limits should depend on VOS voltage which, in turn, depends on SYSCLK, rather than on post-HPRE clock. As a result, lowering timers' clock lowers the max limits - see the screenshots. This does not seem to make sense.
2) Interestingly, AHB1, AHB2, APB1, APB2 and AHB4 clocks do not get the warning.
3) Setting DFSDM1&2 clocks higher than the max allowed 140MHz does not cause any warnings. It is a bit unclear what max DFSDM clock is. In Table 23 on p. 84 DS13195 specifies 140MHz while in Table 107 on p. 162 it states max fDFSDMCLK is fSYSCLK.
4) Watch out! Generated SystemClock_Config() contains this line:
HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
CubeMX 6.2.1 now by default wants to use SMPS power supply. It seems this is a deviation from the previous version.
5) It is not a CubeMX issue but RM0455 33.4.4 (pp. 1161, 1164, 1165) incorrectly states that Manchester clock time should stay within the limits defined by SYSCLK. It should be DFSDMCLK - which may or may not equal SYSCLK.
Tested with STM32H7A3VITx and CubeMX 6.2.1
Max STM32H7A3 clock frequencies are defined in DS13195, Table 23, p. 84
