I2S Clock in CubeIDE Clock Configuration seems unrelated to sample rate?

[exlabs]

Hi,

I am trying to minimise the error between the I2S sampling rate.

You can do this pretty well in the STM32F4 because it has an independent I2SPLL (0.02% error between target sampling rate and actual rate is excellent), this is done by changing the PLLI2S N and R values. However, I do not understand why the 48kHz sample rate needs "I2S clocks (MHz)" to be around 49 MHz. Can someone explain that?

 

[KDJEM.1]

Hello @exlabs;

Could you please precise which STM32F4 devices are you using?

For example if you use a STM32F405 MCU and as mentioned in reference manual RM0090 section 6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)

This register is used to configure the PLLI2S clock outputs according to the formulas:
f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLM)
f(PLL I2S clock output) = f(VCO clock) / PLLI2SR

The error is depend on PLLI2SN and PLLI2SR table 128. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) in RM0090 gives an example values for different clock configurations. Other configurations allowing optimum clock precision are possible.

For maximum I2S main clock, I recommend you to take a look at the STM32MCU datasheet  I2S dynamic characteristics table.

Thank you.

Kaouthar.