floating point and interrupt

[rzong.1]

Hi,

i am using stm32F411 and generate programs with cubeMX.

now I want to use the FPU in main and in interrupt context. Is it possible to use the FPU in interrupt context?

I do not know how CubeMX generated programs handle the FPU context save within interrupt.

[waclawek.jan]

> Is it possible to use the FPU in interrupt context?

Yes.

> I do not know how CubeMX generated programs handle the FPU context save within interrupt.

The processor handles it, and in a rather clever way:

https://static.docs.arm.com/dai0298/a/DAI0298A_cortex_m4f_lazy_stacking_and_context_switching.pdf

JW

[rzong.1]

thanks.

I had a quick view on the paper.

If I use the FPU in an interrupt routine 16 floating point register will be saved on the stack and popped if the routine returns. So that will cost minimum 32 cycles mor than a routine without using the FPU. Is that right?

[Pavel A.]

> So that will cost minimum 32 cycles mor than a routine without using the FPU.

Yep. And more RAM reserved for stack. Everything has its price.

-- pa

[rzong.1]

>Yep. And more RAM reserved for stack. Everything has its price.

easy to pay for me. i have about 10000 multiplications every millisecond. 😉

FPU saves a lot of time in this case, because 1 have one fp mult instead of an integer mult and a shift operation.

thx

[Robmar]

The answer is that there is no FPU context control, and the user must implement in code.

Sadly, and I mean sadly, despite 10 years of posts like yours, STM staff have still not bother to post a code snippet to show how this is done.

If you dig through the RTOS source code you can extract their method.

I am pushing STM to post a routine to handle this efficiently, though as no one replied to your post in 2 years, you probably found a solution or changed to another supplier.

[S.Ma]

In the past, float was discouraged in mobile amd linux within interrupts, and a mitigation using Q31 format was introduced (fractional bit format amd arithmetics). Wondering if things have improved since then... Cordic and FMAT are hw ip separated from core to accelerate computation for motor, etc...

[Pavel A.]

Cortex-M arch has special optimizations for hardware FP. Very clever and convenient, as Jan wrote.

FPU_IRQ does not work for some STM32's, this is in errata.

[Robmar]

I looked at the F407 errata and I didn't see mention of FPU not working in IRQs.

Lazy context doesn't work reliably, and STM are yet to publish an efficient routine to handle FPU context saving and restoring, though I have asked several times.

STM staff publishing an FPU context routine would close this matter for once and all.