Ethernet doesn't work reliable at STM32H743 together with uIP-Stack (HTTP-Trafic)

[Wlad777]

Hello, 

my problem, that uIP-Stack has TCP-Retransmissions with HTTP-trafic. That was observed with Wireshark. The same uIP-Stack works at STM32F7 properly. I'm not sure about Settings in CubeMX with Descriptor Address and Size. My settings are like follows:

with this setting I have followed Error inside uVision5 (compiler version 5):

Spoiler

Error: L6984E: AT section main.o(.ARM.__AT_0x2400060F) has required base address 0x2400060f which is not aligned to section alignment 0x00000004.

Could someone explain how to set Descriptors inside CubeMX properly and get Ethernet work reliable for HTTP trafic?

[SofLit]

Hello @Wlad777 and welcome to the community,

I'm not expert of Ethernet nor the UIP stack, but did you set the correct MPU config for different memory regions used by the stack (heap and descriptors in case of LWIP) as described in this article / especially the section Cortex-M7 configuration?

[Pavel A.]

Why these weird addresses? where have you took this from ?

[Wlad777]

thanks for responses.

[Wlad777]

hello @Pavel A. , it was simply guessed based on size of structs ETH_TxDescListTypeDef and ETH_RxDescListTypeDef found in project. Currently I have changed it to attached screenshot setting and error is gone but the link stability is not the best (same like before). Now I change "RX Descriptor  Length" and observe the Improvement but there is non improvements.

[LCE]

The error message looks like an alignment problem, so you could give some variables the "align 4" attribute, however that works with your compiler.

And check the datasheet for the correct internal SRAM address space for descriptors and buffers.

And, as always: just don't trust that Cube is doing things 100% right.

[Wlad777]

Hello @SofLit , maybe I should activate such MPU config for Descriptors region at STM32H743. I try it out.

[Wlad777]

activation of MPU (for Descriptors region) leads to no improvement.

[Pavel A. · Accepted solution]

It's better to align descriptors and buffers at cache line size which is 32 bytes.

[LCE]

Ah, the cache, the unknown beast to me... :D