CubeMX 6.2 + HAL H7 1.9 limits the ADC clock source to 80MHz in the Clock Configuration tab

[Mikhail Z]

The max ADC clock is 50MHz but the source can be divided by up to 256 so there is no need to limit the source frequency

@Khouloud ZEMMELI​ 

[Khouloud ZEMMELI]

Hello @Mikhail Z​ 

Could you please specify the part number that you are using?

Thanks, Khouloud

[Mikhail Z]

H743ZI​

[Khouloud ZEMMELI · Accepted solution]

Hi @Mikhail Z​ ,

Actually, the maximum ADC frequency depends from the voltage scale value, and according to RM, the Max value cannot exceed the 80Mhz.

In fact, when the Power regulator voltage scale is set to 0 or 1, the Max ADC freq equal to 80MHz, in case when the Power regulator voltage scale is set to 2 or 3, its equal to 40 MHz (for more details, please refer to the Table 59 in the RM).

 

Hope my answer helped you, when your question is answered, please close this topic by choosing Select as Best the reply that answered you, this will help others to find that answer faster.

Thanks for your contribution, Khouloud

[Mikhail Z]

@Khouloud ZEMMELI​ , thank you for clarification. I just don't understand how it is possible to make the 50MHz ADC clock since for STM32H743 ver. V the minimum clock divider is 2 (so for 50MHz at least 100MHz kernel clock is needed).