@Khouloud ZEMMELI , thank you for clarification. I just don't understand how it is possible to make the 50MHz ADC clock since for STM32H743 ver. V the minimum clock divider is 2 (so for 50MHz at least 100MHz kernel clock is needed).
In fig. 202 it looks more like the digitization time is different, but the sampling time is the same. By the way, what is your triggering rate? Did you check that the sampling + digitization time is less than the trigger period?
The manual says that "In regular simultaneous mode, one must convert sequences with the same length and inside a sequence, the N-th conversion in master ans slave must be configured with the same sampling time."
