I'm looking at CubeMX's generation of the linker file (specifically an unconfigured project using the NUCLEO-H7S3L8) and I notice some discrepancies with certain memory region sizes.
According to RM0477, the DCTM - RAM region begins at 0x2000_0000 and ends at 0x0x2003_0000, giving 192 KiB worth of memory. It can be seen in Figure 3 if one happens to have an electron microscope on their workbench.
Yet, CubeMX's linker file says that the DTCM region has a length of 0x0001_0000, which is 64 kibibytes.
__FLASH_BEGIN = 0x08000000;
__FLASH_SIZE = 0x00010000;
__RAM_BEGIN = 0x24000000;
__RAM_SIZE = 0x4FC00;
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
/* Memories definition */
MEMORY
{
RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000
DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000
FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
}RAM and RAM_NONCACHEABLEBUFFER is also weird; it seems to only cover 320 kibibytes, but the collective AXI - SRAM 1, 2, 3, and 4 altogether make up 456 kibibytes according to the RM's diagram. So where is all that memory going? I'm also not sure what RAM_NONCACHEABLEBUFFER even is; is that something for ST's HAL in case it wants to bypass the cache?
More likely than not, I'm interpreting the RM's memory map diagram incorrectly. The product description of the STM32H7S3L8 says this:
STM32H7Sxx8 devices incorporate high-speed embedded memories, 64 Kbytes of user flash memory and 128 Kbytes of system flash memory,and up to 620 Kbytes of RAM (including 128 Kbytes that can be shared between ITCM and AXI, including 64 Kbytes exclusively ITCM, including 128 Kbyte DTCM, including 64 Kbytes exclusively DTCM, including 32 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. To improve application robustness, all memories feature error code correction (one error correction, two error detections).
So is the DTCM memory region in linker file "exclusively DTCM"? What about the other half? How do I make sense of all of this?
