About PhucXDoan

PhucXDoan · 2024-07-22

Today I started to implement DMA for the SDMMC peripheral, and it worked for the most part, but when I got around to doing some sector writes, I started to get CRC-16 mismatches. This was a relatively simple fix, as I was enabling the Data Path State...

PhucXDoan · 2024-07-20

Today I decided to improve the performance of my USB driver by transferring multiple IN packets at a time, instead of one at a time. This in theory would be relatively easy, as I can just configure the IN endpoint's TX-FIFO to have a larger allocatio...

PhucXDoan · 2024-07-15

So far I can do 4-bit wide 24MHz read/write transactions on two microSD cards I have on hand, and I'm looking forward to doubling this to 48MHz. I'm pretty sure the cards I have can support this, as I handle the SWITCH_FUNC command to make sure they ...

PhucXDoan · 2024-07-12

I'm writing my own USB BOT device driver, and I'm receiving the SCSI opcode 0xA1, which isn't defined in SPC or SBC, but rather in the ATA Command Pass-Through specification. Even WireShark doesn't recognize it.What exactly is the significance of thi...

PhucXDoan · 2024-07-06

This is a long one, so sit tight around the campfire, and let me tell you the tale of The Futility of EPENA.Several days ago, I began to implement a Mass Storage interface for my own USB stack, equipped with a Bulk IN and OUT endpoint. The first thin...

PhucXDoan · 2024-07-12

I believe I've figured out the puzzle, and it's quite multi-faceted.First, I believe I made an error in my original setup, since I can't reproduce it now. I likely accidentally configured the wrong endpoint, that is, setting the PKTCNT and XFRSIZ for...

PhucXDoan · 2024-07-08

Not sure how traces in WireShark will help, as it's pretty much identical to what would happen if I had configured the OUT transfer properly as described in the RM ("Generic non-isochronous OUT data transfers"). What I'd expect to happen is for the O...

PhucXDoan · 2024-07-06

wMaxPacketSize is set appropriately, actually, but it's still possible something funny is happening on the bus that isn't revealed in WireShark side of things, or I really did configure things weird and it have been miraculously working just fine. I'...

PhucXDoan · 2024-06-28

After a mild crisis, I managed to resolve a bug relating to this poorly documented STSPHST bit, to which I'll describe here for any future tinkerers who are also in the same position as I am:As it turns out, the USB core blocks any further receptions...

PhucXDoan · 2024-06-12

I think I pinned down the issue: it was the fact that my host machine -- for some reason -- always expects the default endpoint to have a maximum size of 64 right after plugging in the device, even if the device doesn't support it. This ends up appea...

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(SDMMC) The Journey of: How exactly does a CRC-16 mismatch get signaled in the SD Bus Protocol?

Another USB_OTG_FS Quirk: The 3-bit counter of IN endpoints.

Design Considerations for High-speed SDMMC Transactions?

Why is SCSI opcode 0xA1 (ATA_PASS_THROUGH) sent?

More USB Shenanigans : The Futility of EPENA.

Re: More USB Shenanigans : The Futility of EPENA.

Re: More USB Shenanigans : The Futility of EPENA.

Re: More USB Shenanigans : The Futility of EPENA.

Re: USB_OTG_FS - The STSPHST bit - To bit, or not to bit, that is the question.

Re: How to perform a control IN endpoint transfer with the USB OTG FS core?