Clock configuration for Nucleo-H7A3
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‎2020-02-12 04:19 AM
Hello,
I started an empty project on CubeMX V5.5 (just updated) for a Nucleo-H7A3ZI,
I noticed that the clock default configuration for this board has a 64MHz clock.
If I change the multiplier on the PLL1 from x16 to x70 to get the max allowed 280MHz, I get an error on the 280MHz clock for AHB1,2 peripheral's clock.
However from the datasheet AHB clock can go up to 280MHz
Is this just a bug because this family has just appeared?
Regards,
Marco
- Labels:
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RCC
-
STM32CubeMX
-
STM32H7 Series
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‎2020-02-18 01:06 AM
Hello @Community member​
Thanks for the feedback,
It will be fixed next CubeMX version.
Best regards,
Nesrine
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‎2020-02-20 03:51 AM
Hi Nesrine,
thanks.
Something else that might also interest the community: is there a release date for it yet?
Thanks,
Marco
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‎2020-02-20 04:18 AM
​next week.
Regards,
Nesrine
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‎2020-02-24 04:27 AM
Hi Nesrine
I've installed the new version, the CubeMX is able to configure the clocks for 280MHz,
however the code generated for the CubeIDE seems to had 2 bugs, can you please confirm:
Original code for SystemClock config:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
LL_FLASH_SetLatency(FLASH_LATENCY_7);
if(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_7)
{
Error_Handler();
}
LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
LL_RCC_HSE_EnableBypass();
LL_RCC_HSE_Enable();
/* Wait till HSE is ready */
while(LL_RCC_HSE_IsReady() != 1)
{
}
LL_RCC_HSI48_Enable();
/* Wait till HSI48 is ready */
while(LL_RCC_HSI48_IsReady() != 1)
{
}
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
LL_RCC_PLL1P_Enable();
LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_8_16);
LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
LL_RCC_PLL1_SetM(1);
LL_RCC_PLL1_SetN(70);
LL_RCC_PLL1_SetP(2);
LL_RCC_PLL1_SetQ(4);
LL_RCC_PLL1_SetR(2);
LL_RCC_PLL1_Enable();
/* Wait till PLL is ready */
while(LL_RCC_PLL1_IsReady() != 1)
{
};
/* Intermediate AHB prescaler 2 when target frequency clock is higher than 80 MHz */
LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_1);
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_2);
LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2);
LL_SetSystemCoreClock(280000000);
/* Update the time base */
if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
{
Error_Handler();
};
LL_RCC_SetUSARTClockSource(LL_RCC_USART234578_CLKSOURCE_PCLK1);
LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_HSI48);
}
I think line 47 is wrong (SetAHBPrescaler is used in line 50), I believe it should be something like:
LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
Also a line must be included to increase the programming delay (according to table 15 of the reference manual)
something like this after setting the latency (before line 13?):
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_3);
Am I correct?
Thanks
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‎2020-02-24 05:29 AM
Hello @Community member​
Could you please send me your .ioc file.
Regards,
Nesrine
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‎2020-02-24 05:55 AM
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‎2020-02-24 06:06 AM
Hi @Community member​
Function LL_RCC_SetAHBPrescaler cannot accept argument type LL_RCC_SYSCLK_DIV_2.
It should be LL_RCC_AHB_DIV_2.
For this line, __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_3); I will check it with the development team then i will tell you.
Regards,
Nesrine
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‎2020-02-24 06:14 AM
The clock is working ok because the AHBPrescaler is by default set to 1, however the programming delay is not set according to table 15, the (default) value for WRHIGHFREQ: Flash signal delay is 1 instead of 3.
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‎2020-02-24 07:31 AM
Just a note: the previous version of CubeMX (5.5) was generating line 47 like this (which, as you say, would be wrong):
/* Intermediate AHB prescaler 2 when target frequency clock is higher than 80 MHz */
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
That is why I was suggesting to replace the LL_RCC_SetAHBPrescaler to LL_RCC_SetSysPrescaler.
I see now that the code divides the clock temporarily just before selecting the source for the sysclock, then it sets again the division to 1