2022-11-09 10:39 AM
On the data sheet block diagram, it shows it to be 45MHz - APB1. However, on the clock configuration screen on STM32CUBEIDE there are two APB1 clocks - the APB1 Peripheral Clock, and the APB1 Timer Clock. Naturally I would assume it's the "timer clock" but I want to be sure.
2022-11-09 12:02 PM
in Cube clock tree -> you can see it : timer clk is 1x or 2x APBx clk .
most times 2x .
2022-11-09 01:41 PM
While the APB bus clock is still used to read/write the timer's registers and that's indeed max 45MHz, the timer internally uses a different clock, the timer clock, as AScha said above.
The primary source of information is not Cube/CubeMX, but the RM, in this case the RCC chapter - note the clock diagram there, together with its footnotes.
JW