STM32F767 DTCM cache - static variables

[Petr3]

Hello,

i have enabled D-cache and I-cache and im trying to place static variables into D-cache:

__attribute__((section(".dtcmram"))) __attribute__((aligned(32))) static float32_t FFTOutput_average[MAX_FFT_PRINT_SIZE] = {0};

I updated linker script as follows:

/*RAM      (xrw)   : ORIGIN = 0x20000000,   LENGTH = 512K*/
  ITCMRAM  (xrw)    : ORIGIN = 0x00000000,   LENGTH = 16K
  DTCMRAM  (xrw)   : ORIGIN = 0x20000000,   LENGTH = 128K
  RAM      (xrw)   : ORIGIN = 0x20020000,   LENGTH = 384K
  FLASH    (rx)    : ORIGIN = 0x08000000,   LENGTH = 2048K
  SDRAM0	(rwx)	: ORIGIN = 0x60000000,	LENGTH = 2048K
  SDRAM1	(rwx)	: ORIGIN = 0x60200000,	LENGTH = 2048K
  SDRAM2	(rwx)	: ORIGIN = 0x60400000,	LENGTH = 2048K
  SDRAM3	(rwx)	: ORIGIN = 0x60600000,	LENGTH = 2048K

...

  .dtcmram (NOLOAD) :
  {
  	. = ALIGN(4);
    *(.dtcmram)
    *(.dtcmram*)
  } >DTCMRAM

  .itcmram :
  {
  	. = ALIGN(4);
    *(.itcmram .itcmram.*)
  } > ITCMRAM

but the linker still places static variable into RAM region. I think the problem is in .bss which is located in RAM section but i dont know how to add it into DTCMRAM.

[AScha.3]

Hi,

>and im trying to place static variables into D-cache

No, you cannot place anything into D-cache. Cache is controlled by its cache-controller --> enable , thats it.

What you want to gain ? more speed ? Anyway, using core-coupled memory is accessed without any wait , so "more speed" is not possible.

So you could use DTCMRAM for data, at max. speed, cache on or off changes nothing here.

I use (on H7 , similar to F7 ) all :

Try with mod linker script, here from my xxx_flash.ld :

  /* Initialized data sections goes into RAM, load LMA copy after code */
  .data :
  {
    . = ALIGN(4);
    _sdata = .;        /* create a global symbol at data start */
    *(.data)           /* .data sections */
    *(.data*)          /* .data* sections */
    *(.RamFunc)        /* .RamFunc sections */
    *(.RamFunc*)       /* .RamFunc* sections */

    . = ALIGN(4);
    _edata = .;        /* define a global symbol at data end */
  } >DTCMRAM AT> FLASH   /* war >RAM_D1 AT> FLASH   */

  /* Uninitialized data section */
  . = ALIGN(4);
  .bss :
  {
    /* This is used by the startup in order to initialize the .bss section */
    _sbss = .;         /* define a global symbol at bss start */
    __bss_start__ = _sbss;
    *(.bss)
    *(.bss*)
    *(COMMON)

    . = ALIGN(4);
    _ebss = .;         /* define a global symbol at bss end */
    __bss_end__ = _ebss;
  } >DTCMRAM				/* war >RAM_D1   */

[Petr3]

Yes i have enabled both cashes in *.ioc due to external SDRAM used for LTDC screen buffer. The first bank is used for screen buffer. When i want to access into second bank the STM goes into hard fault handler. The third bank im using for dynamic bitmap(custom graphic). The fourth bank is empty but i need fast access to the variables. So i decided to use space in D-cache.

I edited linker script as you proposed but it is still placed into RAM.

[mƎALLEm]

Hello,

You cannot place anything in the cache by hand. It's not a memory mapped device in the MCU.

You need to enable the cache and place your data in a cacheable region (need to configure the MPU if it was not a cacheable region by default like SDRAM at 0xAXXX XXXX). It follows this default ARM MPU attributes:

As you are using the SDRAM at the address 0x6XXX XXX. If you enabled the cache it's definitely cacheable.

DTCM (as Data Tightly Coupled Memory) is not the D-cache it's a RAM that doesn't profit from the cache. Enabling or disabling the cache doesn't change the access performance to the memory.

I invite you to refer to the application note AN4667 "STM32F7 Series system architecture and performance"

[Petr3]

Hello @mƎALLEm,

sorry for bad expression, i meant DTCMRAM. I dont understand these caches - i didnt use it never before. I thought that enabling of cache speeds up access for the screen buffer in external SDRAM via FMC. So i enabled it. In some moment i find out, that i dont have 512kB RAM but only 384kB. The DTCMRAM consumes 128kB and ITCMRAM 16kB. When i instantiated static array of floats, the program starts causing bad behaviour because i overlap by this static array from 384kB SRAM into DTCMRAM section. When i disabled cache i've got again 512kB SRAM and program worked as expected. But im not sure if TouchGFX has the same speed access into external SDRAM with disabled caching in comparison cache was enabled(im using 800x480 16bpp TFT over LTDC). I have added MPU regions for whole 8MB of external SDRAM and 4x2MB for each bank.

Im able to place global variables into DTCMRAM when i added DTCMRAM into linker script but im not able to place here variables defined as static. I want to declare these variables in internal RAM because program periodically computes FFT and DSP filternig stuff and im not sure if FMC is able to handle this together with display buffering without artefacts on TFT screen.

So what do you recomend for this applicacion? Stay with disabled cache and have 512kB space of SRAM or enable cache and use 384kB space of SRAM and 128kB space of DTCMRAM?

[AScha.3]

You can check in mem.details , where its going to be :

Then you see: is your linker script as you want it - or not.

[TDK]

See here for correct syntax. You're close, but use "dtcmram" not ".dtcmram".

OpenSTM32 Community Site | Using CCM Memory

char in_ccram_buffer[1024] __attribute__((section("ccmram")));