SPI shift register

[ajimathew]

      In the block diagram of SPI ,There were 2 FIFOs (Rx and Tx) but only one shift register . In case of Full- duplex communication simultaneous transmission and reception will happen. How one shift register handles both transmitting and recieving??

[TDK · Accepted solution]

You shift a bit out at the same time you shift a new one in. For an 8-bit register, it would initially store 8 TX bits, then 7 TX bits and 1 RX bit, etc, until it eventually stores all 8 RX bits and shifts those into the RX FIFO and grabs a new byte from the TX FIFO.