PSSI SFR not available while debugging (STM32H730)

[EKoec]

Hey there. I am developing an application which uses the PSSI interface of the STM32H730. But while debugging the registers are not available in the SFR view. Any ideas?

[Markus GIRDLAND]

Hello there!

STM32CubeIDE only reads an .svd file to display these registers. I will submit a ticket to the responsible team for further analysis and possible correction.

If this is urgent then you can manually add it in the .svd file by default located at:

C:\ST\STM32CubeIDE_1.6.0\STM32CubeIDE\plugins\com.st.stm32cube.ide.mcu.productdb.debug_1.6.0.202102151443\resources\cmsis\STMicroelectronics_CMSIS_SVD\STM32H73x.svd

Thanks for bringing it to our attention!

[EKoec]

Thanks for your quick reply. If i do a

grep -ri PSSI_CFG

in the respective folder it doesn't return anything so it seems to me the interface registers are missing from all svd files.

[Markus GIRDLAND]

You're correct. The information seems to be missing from the .svd files. I went ahead and created a ticket (internal BZ#107070). The team responsible for the updating of these files have been assigned to the ticket.

[EKoec · Accepted solution]

Adding..

<peripheral>
      <name>PSSI</name>
      <description>Parallel synchronous slave interface </description>
      <groupName>PSSI</groupName>
      <baseAddress>0x48020400</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
 
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>PSSI control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x40000000</resetValue>
          <fields>
            <field>
              <name>OUTEN</name>
              <description>Data direction selection bit</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAEN</name>
              <description>DMA enable bit</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DERDYCFG</name>
              <description>Data enable and ready configuration</description>
              <bitOffset>18</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>ENABLE</name>
              <description>PSSI enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>EDM</name>
              <description>Extended data mode</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>RDYPOL</name>
              <description>Ready (PSSI_RDY) polarity</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DEPOL</name>
              <description>Data enable (PSSI_DE) polarity</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>CKPOL</name>
              <description>Parallel data clock polarity</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
 
        <register>
          <name>PSSI_SR</name>
          <displayName>PSSI_SR</displayName>
          <description>PSSI status register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0X00000000</resetValue>
          <fields>
            <field>
              <name>RTT1B</name>
              <description>FIFO is ready to transfer byte</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>RTT4B</name>
              <description>FIFO is ready to transfer 4 byte</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
 
        <register>
          <name>PSSI_RIS</name>
          <displayName>PSSI_RIS</displayName>
          <description>PSSI raw interrupt status register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0X00000000</resetValue>
          <fields>
            <field>
              <name>OVR_RIS</name>
              <description>Data buffer overrun/underrun raw interrupt status</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
 
        <register>
          <name>PSSI_IER</name>
          <displayName>PSSI_IER</displayName>
          <description>PSSI interrupt enable register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0X00000000</resetValue>
          <fields>
            <field>
              <name>OVR_IE</name>
              <description>Data buffer overrun/underrun interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
 
        <register>
          <name>PSSI_MIS</name>
          <displayName>PSSI_MIS</displayName>
          <description>PSSI masked interrupt status register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0X00000000</resetValue>
          <fields>
            <field>
              <name>OVR_MIS</name>
              <description>Data buffer overrun/underrun masked interrupt status</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
 
        <register>
          <name>PSSI_ICR</name>
          <displayName>PSSI_ICR</displayName>
          <description>PSSI clear interrupt status register</description>
          <addressOffset>0x14</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0X00000000</resetValue>
          <fields>
            <field>
              <name>OVR_ISC</name>
              <description>Data buffer overrun/underrun interrupt status clear</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
 
        <register>
          <name>PSSI_DR</name>
          <displayName>PSSI_DR</displayName>
          <description>PSSI data register</description>
          <addressOffset>0x28</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0X00000000</resetValue>
          <fields>
            <field>
              <name>BYTE3</name>
              <description>Data byte 3</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>BYTE2</name>
              <description>Data byte 3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>BYTE1</name>
              <description>Data byte 3</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
            <field>
              <name>BYTE0</name>
              <description>Data byte 3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
 
      </registers>
    </peripheral>

... to

STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.productdb.debug_1.xxxxx/resources/cmsis/STMicroelectronics_CMSIS_SVD/STM32H73x.svd

seems to do the trick, no guarantee for correctness, though.

[Markus GIRDLAND]

As a quick update:

This has been corrected and will be part of the next release of STM32CubeIDE.